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The QA Firmware Engineer will validate COSMOS Firmware and SDKs for Astera Labs' SoCs and systems products, develop test plans, procedures, and execute tests, and analyze test results. They will work closely with development to ensure implementation quality.

As a Principal Design Verification Engineer, you will lead the functional verification of designs using your expertise in PCIe, CXL, DDR, and Ethernet protocols. Responsibilities include developing verification plans, writing test sequences, executing tests, and collaborating with RTL designers to debug issues. You will leverage your coding skills and knowledge of verification methodologies to ensure high-quality silicon products.

The Senior Formal Verification Engineer will be responsible for developing and implementing formal verification abstractions, models, and assertions to identify critical logic components and ensure design correctness. The role involves collaborating with designers, performing assertion-based model checking, and participating in design reviews to enhance performance and design interfaces.

As a Principal Physical Design Engineer at Astera Labs, you will oversee the planning and execution of the design of connectivity ASICs for leading cloud service providers. You will coordinate with diverse teams, ensuring timely delivery of complex designs, and utilize your expertise in timing constraints and physical design tools to drive projects from architecture to GDSII.

The Senior Digital Design Engineer will develop micro-architecture and front-end circuit design including RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. Responsibilities include hands-on design work and ownership of designs from architecture to production.

As a Signal/Power Integrity Engineer, you will be responsible for SI planning, design, modeling, simulation, and lab validation for high-speed connectivity products. The role involves creating validation plans, conducting experiments, analyzing results, and collaborating with internal teams to ensure product robustness.

As a Principal Physical Design Engineer at Astera Labs, you will oversee the planning and execution of design for connectivity ASICs. Collaborating closely with teams in the design, verification, and engineering operations, you will ensure timing constraints and methodologies are maintained for complex silicon products.