Principal Signal/Power Integrity Engineer

Posted 10 Days Ago
Be an Early Applicant
Santa Clara, CA
170K-250K Annually
Senior level
Big Data • Information Technology
The Role
As a Principal Signal/Power Integrity Engineer, you will execute SI planning, modeling, simulation, and validation for high-speed interconnects in AI and cloud infrastructure products. Responsibilities include formulating validation plans, conducting experiments, and ensuring compliance with specifications while collaborating with internal customers for system robustness.
Summary Generated by Built In

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. 

At Astera Labs, we seek motivated SI/PI and System Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. You will also formulate a comprehensive system validation plan and design experiments to root cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

 

Basic Qualifications:

  • Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
  • 5+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and Networking applications.
  • 10+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
  • We have proven track record with defining hardware system constraints and high-speed technology roadmaps.
  • Cross-functional design mentality with silicon design community to develop systems.
  • Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.
  • Proven track record solving problems independently, preferably as a tech lead.
  • Entrepreneurial, open-minded behavior, and can-do attitude.
  • Authorized to work in the US and start immediately.

 

Required experience:

  • Familiar with SI and PI design challenges for high-speed interconnects
  • Hardware product design experience in networking, compute, or RF.
  • 2D and 3D simulation experience with Cadence/Mentor/Ansys/ADS/etc. toolsets
  • EM modeling of connector structures
  • High-speed SERDES measurement, channel simulation, and equalization
  • Expertise in DDR4/5 memory bus designs
  • Expertise in multi-level and NRZ signaling, COM, BER, jitter analysis
  • Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
  • Working knowledge of PCB fabrication limits and trade-offs
  • PI experience a bonus.
  • Familiar with industry-standard such as IEEE802.3
  • Familiarity with PCIe5/6 and CXL specs, especially Electrical Compliance sections
  • Working knowledge of key, high-speed design blocks such as PLLs, DFE, Tx EQ
  • Experience in system testing, characterization, margin analysis, and optimization of high-speed PCIe/CXL data links over long and short channels
  • In-depth understanding of DDR 4/5 protocols and JEDEC Standard. Hands-on experience with DDR4/5 post-silicon electrical validation.
  • Proficiency in using high-speed lab equipment such as BERT, Oscilloscope, and VNA
  • Strong debug, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

The base salary range is $170,000 USD - $250,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Top Skills

Electrical Engineering
The Company
HQ: Santa Clara, CA
148 Employees
On-site Workplace
Year Founded: 2017

What We Do

Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center.

Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning.

The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

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