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8 Days Ago
Austin, TX, USA
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Sr. Principal Software Engineer will focus on developing high-performance software tools for Design For Test (DFT) and Automatic Test Pattern Generation (ATPG). Responsibilities include software architecture research, algorithm optimization, and collaboration with engineers to deliver reliable and scalable solutions.
8 Days Ago
Austin, TX, USA
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The role involves developing reliable and scalable software tools for Design For Test and Automatic Test Pattern Generation. The engineer will collaborate with a team to create high-performance software and research solutions aimed at improving software architecture and efficiency.
8 Days Ago
Austin, TX, USA
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Senior Software Engineer will work on developing an AI graph compiler to optimize neural networks for execution on embedded platforms. Responsibilities include innovating optimization techniques and algorithms for mapping neural networks onto Tensilica Xtensa processors and specialized accelerators.
8 Days Ago
San Jose, CA, USA
8,216 Employees
120K-224K Annually
Mid level
8,216 Employees
120K-224K Annually
Mid level
Cloud • Hardware • Software • Semiconductor
As a Principal Application Engineer, you will engage with customers to identify opportunities, evaluate criteria, and convert opportunities into business effectively utilizing Cadence tools. You will work closely with R&D and Product Engineering for new features and address production issues, requiring strong analytical and customer communication skills.
8 Days Ago
Austin, TX, USA
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The successful applicant will be responsible for designing and developing high-performance, low-power Network on Chip products, focusing on hardware architecture, micro-architecture definition, and RTL design.
8 Days Ago
Austin, TX, USA
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
Design state-of-the-art DDR memory controllers for various applications, architect solutions for DDR controller features, and collaborate with project teams to enhance development processes and productivity.
8 Days Ago
Austin, TX, USA
8,216 Employees
132K-244K Annually
Senior level
8,216 Employees
132K-244K Annually
Senior level
Cloud • Hardware • Software • Semiconductor
As a Principal Product Engineer at Cadence, you will work closely with R&D and engineering teams to enhance advanced chip design tools. Your responsibilities include characterizing IP, analyzing various Liberty formats, conducting customer engagement, running benchmarks, and developing automation using scripting languages.
8 Days Ago
San Jose, CA, USA
8,216 Employees
71K-133K Annually
Entry level
8,216 Employees
71K-133K Annually
Entry level
Cloud • Hardware • Software • Semiconductor
The Application Engineer will support the sales team by providing technical sales and customer support in silicon design, using EDA tools. The role involves hands-on training in various areas such as design, verification, and software development over a one-year rotational program.
8 Days Ago
San Jose, CA, USA
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Sr Hardware Sales Executive at Cadence will drive hardware sales growth by working with account executives and engineering teams. Responsibilities include managing sales efforts for hardware-assisted verification solutions, engaging in business development, negotiating contracts, and educating sales teams in the semiconductor and electronics space.
8 Days Ago
Austin, TX, USA
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Senior RTL Design Architect at Cadence will be responsible for CPU and interface IP selection, digital design, creating detailed micro-architecture specifications, and collaborating with verification teams. The role emphasizes RTL development and physical design deliverables, ensuring timely IP delivery while working with multidisciplinary teams.
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