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The Solutions Engineer at Cadence will assist customers with their Digital Implementation challenges using Cadence's technology. Responsibilities include driving pre-sales and post-sales activities, collaborating with R&D to develop new technologies, solving complex technical issues related to Timing/Noise/Variation characterization, and automating performance analysis and optimizations.

The role involves driving architectural and performance improvements in Xcelium build, requiring expertise in HDL build and simulation, particularly focusing on HDL verification using System Verilog and VHDL.

The Design Engineer position at Cadence involves working on the next generation emulation processors as part of the Palladium ASIC development team. Responsibilities include RTL development of complex ASIC/SoC, using Verilog and SystemVerilog, understanding ASIC design flow, and working with design tools like Incisive, NCSim, Genus, Design Compiler, STA, power analysis, Lint, and CDC. Exposure to major IP and protocols like SERDES, PCIe, and DDR4 is also required. The position offers annual salary range of $131,600 to $244,400 with additional incentive compensation and benefits.