At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Proficient in Developing STA and EMIR solutions at Full-Chip at Block Level.
(1) Hierarchical STA Flows
(2) Top Block Constraint validation and budgeting
(3) Full chip clock propagation
(4) ETM and power view model generation and validation
(5) Timing and Power Signoff checks to ensure final tapeout quality
(6) PVT Corner selection and margining for Global/Local/Library/Process/Design variations to ensure silicon success
(7) Proficient in scripting for such checks and developing flows for other members to use.
(8) Build regression suite to validate versions and features
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Top Skills
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
