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19 Hours Ago
Boston, MA, USA
552 Employees
Senior level
552 Employees
Senior level
Software
The Debug, Trace and Profiling Architect at SiFive will define platform requirements and architectural features for debug, trace, and profiling solutions. They will engage with customers to understand needs, interact with various architectural teams, and develop microarchitecture specifications in a collaborative environment.
19 Hours Ago
Boston, MA, USA
552 Employees
Senior level
552 Employees
Senior level
Software
The Functional Safety Architect will contribute to SiFive's FuSa/RAS solution portfolio, ensuring seamless integration across IPs and collaborating with engineering and product teams to derive requirements for failure detection and response solutions.
19 Hours Ago
Austin, TX, USA
552 Employees
Junior
552 Employees
Junior
Software
The Verification Engineer at SiFive will ensure the fidelity of new RISC-V based CPU IPs by adopting advanced verification methodologies. Responsibilities include creating test plans, executing tests, and ensuring design quality through coverage metrics, while working alongside a high-performance CPU team on components such as Frontend and Execution Units.
19 Hours Ago
Austin, TX, USA
552 Employees
187K-326K Annually
Senior level
552 Employees
187K-326K Annually
Senior level
Software
The Principal System and Software Architect will design and implement RISC-V computing platforms while collaborating cross-functionally to deliver advanced CPU cores and systems. Responsibilities include developing software for SiFive hardware features, creating architectural specifications, and planning complex projects within a cross-functional engineering team.
19 Hours Ago
Boston, MA, USA
552 Employees
Senior level
552 Employees
Senior level
Software
The Fusa/RAS Architect will contribute to creating a robust FuSa/RAS solution portfolio, collaborate with engineering teams for optimal implementation, analyze requirements to detect failures, and support product teams to identify customer needs in functional safety and RAS.
19 Hours Ago
Austin, TX, USA
552 Employees
Senior level
552 Employees
Senior level
Software
The Sr. Staff Verification Engineer will verify the functionality of RISC-V based CPU IPs, ensuring design fidelity through test planning, execution, and coverage metrics. Responsibilities include adopting advanced methodologies and collaborating on high-performance Out-of-Order Core components for diverse applications such as 5G and IoT.
3 Days Ago
Santa Clara, CA, USA
552 Employees
166K-202K Annually
Senior level
552 Employees
166K-202K Annually
Senior level
Software
The Sr. Technical Program Manager will coordinate and lead cross-functional teams throughout the product life cycle, focusing on CPU core design and related tools. Responsibilities include developing project plans, tracking program execution, participating in technical discussions, and enhancing program management processes. The role requires excellent communication and project management skills, alongside experience with CPU technology and related software.
4 Days Ago
Santa Clara, CA, USA
552 Employees
149K-182K Annually
Senior level
552 Employees
149K-182K Annually
Senior level
Software
Develop and enhance debugging and profiling tools for SiFive RISC-V processors. Responsibilities include improving command line and IDE tools, engaging with teams for new feature refinement, implementing best software development practices, and providing customer support as needed.
7 Days Ago
Santa Clara, CA, USA
552 Employees
194K-237K Annually
Senior level
552 Employees
194K-237K Annually
Senior level
Software
SiFive seeks a technical lead to design industry-leading debug, trace, and performance monitoring hardware for RISC-V architectures. Responsibilities include architecting and implementing hardware, collaborating with performance and software teams, and integrating designs into existing frameworks.
9 Days Ago
Santa Clara, CA, USA
552 Employees
194K-237K Annually
Senior level
552 Employees
194K-237K Annually
Senior level
Software
The Senior Staff Software Architect will lead the design and implementation of RISC-V computing platforms, engage in software and hardware architecture, and collaborate with global engineering teams to develop advanced computing systems focusing on performance and reliability.
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