Debug/Trace/Monitoring RTL Design Lead

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

SiFive is seeking a hardware design technical lead who is passionate about designing industry-leading debug, trace and performance monitoring IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating a highly customizable line of processor cores with fast time-to-market by designing the hardware as highly configurable generators. We're leveraging technology and ideas from the software industry to execute hardware design with the speed
and agility of software development.

We build and maintain our RISC-V processor subsystem IP using the Chisel hardware construction library embedded in the Scala language,
and are seeking a motivated individual to lead enhancement of our existing debug/trace/monitoring hardware as well as development of new

capabilities in this area.

The successful applicant will address the following challenges:
- Designing the best debug, trace and performance monitoring hardware in the world, based on the revolutionary open RISC-V and TileLink architectures
- Mastering the art of designing hardware as configurable generators in a domain-specific software language for elaborating digital logic
- Working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance

Join us, and surf the RISC-V wave with SiFive!

Job Responsibilities:

• Architect, design and implement debug, trace and performance monitoring hardware

• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification

• Implement RTL generators such that elements self-configure to optimally

• Design extensive configurability in as a first-class consideration

• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification test benches and tests, and packaged software.

• Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans

• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design

Position Requirements:

• Knowledge of debug, trace and performance monitoring architecture and concepts

• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL

• Attention to detail and a focus on high-quality design

• Ability to work well with others and a belief that engineering is a team sport

• Knowledge of at least one object-oriented and/or functional programming language

• Knowledge of one or more of: Chisel/Scala, RISC-V architecture, Git/Jira/Confluence is a plus

• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/monitoring hardware for high-performance processors

• MS/PhD in EE, CE, CS or a related technical discipline

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

$193,500.00-$236,500.00

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

United States of America

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

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