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19 Days Ago
Folsom, CA, USA
2,298 Employees
139K-215K Annually
Senior level
2,298 Employees
139K-215K Annually
Senior level
Semiconductor
The Staff SoC Design Engineer will enhance storage capabilities by developing and optimizing prototype SSD controllers, integrating third-party IP for the HBM memory subsystem, and working closely with verification and physical design teams to ensure timing and functional coverage.
19 Days Ago
Folsom, CA, USA
2,298 Employees
139K-215K Annually
Senior level
2,298 Employees
139K-215K Annually
Senior level
Semiconductor
Develop verification environments for HBM memory subsystems in SoC design. Create verification plans, generate test cases, and develop coverage models. Collaborate with designers and architects for sign-off on verification requirements while ensuring a successful verification flow and tool usage.
19 Days Ago
San Jose, CA, USA
2,298 Employees
177K-283K Annually
Senior level
2,298 Employees
177K-283K Annually
Senior level
Semiconductor
The Senior Staff Engineer will define architectures of NPUs for AI data center applications, develop new low power and high-performance designs, and work with software architects to create optimized solutions. Additionally, they will collaborate with design verification teams for debugging and coverage targets.
19 Days Ago
San Jose, CA, USA
2,298 Employees
208K-332K Annually
Expert/Leader
2,298 Employees
208K-332K Annually
Expert/Leader
Semiconductor
As a Principal Engineer, you will drive the architectural definition of NPUs for AI applications, develop new architectures for low power and high performance, and lead trade-off analysis. Collaborating closely with teams, you will optimize the prototype controller for mass production and ensure debug coverage.
19 Days Ago
San Jose, CA, USA
2,298 Employees
162K-258K Annually
Senior level
2,298 Employees
162K-258K Annually
Senior level
Semiconductor
The Senior Manager of SoC Products and Solutions Planning is responsible for defining product roadmaps for memory solutions and ensuring alignment with business objectives. Key responsibilities include market research, customer engagement, executing go-to-market strategies, and analyzing product usage for improvement. The role involves leadership and collaboration across various departments to enhance customer satisfaction and drive product growth in AI/ML workloads.
19 Days Ago
San Jose, CA, USA
2,298 Employees
Senior level
2,298 Employees
Senior level
Semiconductor
The IP Operations Specialist supports the IP Group by managing the global patent portfolio, working on patent prosecution, collaborating with legal teams, tracking objectives, and optimizing workflows. This includes analyzing data, improving processes, and managing budgets while fostering effective communication across departments.
19 Days Ago
San Jose, CA, USA
2,298 Employees
153K-237K Annually
Senior level
2,298 Employees
153K-237K Annually
Senior level
Semiconductor
As a Staff Engineer in DRAM, you will develop and optimize DRAM architecture, lead design specifications, conduct performance analysis, and collaborate with cross-functional teams. You will also work on power consumption reduction methods while interacting with internal and external customers.
19 Days Ago
San Jose, CA, USA
2,298 Employees
177K-283K Annually
Expert/Leader
2,298 Employees
177K-283K Annually
Expert/Leader
Semiconductor
The Senior Staff Engineer for DRAM will lead the architecture development and design optimization for next-generation DRAM solutions. Responsibilities include developing test plans, analyzing performance, collaborating with cross-functional teams, and enhancing power efficiency for DRAM products.
19 Days Ago
Folsom, CA, USA
2,298 Employees
139K-215K Annually
Senior level
2,298 Employees
139K-215K Annually
Senior level
Semiconductor
The Staff Engineer will enhance SSD capabilities by developing prototype controllers, defining hardware architecture, performing RTL implementation, integrating third-party IPs, and analyzing power consumption in data center storage chips. They will collaborate with teams on design verification, timing constraints, and static timing analysis.
19 Days Ago
San Jose, CA, USA
2,298 Employees
137K-213K Annually
Senior level
2,298 Employees
137K-213K Annually
Senior level
Semiconductor
The Staff Engineer will oversee DRAM Customer Quality by managing product quality and reliability issues, coordinating failure analysis, communicating with Tier 1 customers, and ensuring compliance with quality requirements. The role involves collaboration with engineering teams and the creation of reports to track technical issues.
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