Get the job you really want.

Top Tech Jobs & Startup Jobs

Codasip Logo
Codasip

Hardware Verification Engineer

Yesterday
Heraklion, GRC
Mid level
Mid level
Hardware • Automation
As a Hardware Verification Engineer at Codasip, you will verify RISC-V processors, create and maintain verification plans, automate tests, design solutions for process automation, and improve technologies through innovative ideas. Communication in English is essential due to the distributed nature of the team.
Top Skills: C++Python
Codasip Logo
Codasip

RTOS Engineer

Yesterday
2 Locations
Senior level
Senior level
Hardware • Automation
As an RTOS Engineer at Codasip, you will customize firmware, develop low-level software in C/C++, and enhance real-time operating systems for RISC-V CPU cores. You will support processor design teams, contribute to software innovation, and engage in both short and long-term projects. Strong embedded software development experience and a flexible approach are required.
Top Skills: CC++Rust
Junior
Hardware • Automation
As a CPU Design Engineer, you will design and develop next-generation CPU architectures, focusing on Out-of-Order cores and memory subsystems. Responsibilities include working on complex designs, collaborating with cross-functional teams, and utilizing proprietary tools like CodAL. You will also optimize modules for specific power, performance, and area (PPA) targets while applying your knowledge of hardware description languages and design synthesis flows.
Top Skills: PythonRisc-VShellSystemverilogTclVerilog
Codasip Logo
Codasip

Junior Hardware Verification Engineer (CZ)

Yesterday
Brno, Město Brno, Jihomoravský, CZE
Entry level
Entry level
Hardware • Automation
As a Junior Hardware Verification Engineer at Codasip, you will ensure the quality and reliability of RISC-V processors by creating a robust verification environment, developing automated tests, and collaborating with design teams to meet functional requirements.
Top Skills: BashPythonSystemverilogTclVerilogVhdl
Codasip Logo
Codasip

Senior LLVM Compiler Engineer - CPU

Yesterday
3 Locations
Senior level
Senior level
Hardware • Automation
The Senior LLVM Compiler Engineer will customize and optimize LLVM compilers for embedded CPU cores, support software optimization, provide compiler expertise for microarchitectural design, and explore novel compiler technologies. The engineer will work on projects related to RISC-V technology and engage in both short-term and long-term strategic product development.
Top Skills: CC++LlvmRust
Codasip Logo
Codasip

Senior/Principal Verification Engineer (CPU/RISC-V)

Yesterday
Heraklion, GRC
Senior level
Senior level
Hardware • Automation
The Senior/Principal Verification Engineer will lead the verification team in developing strategies, architectures, and test plans for CPU microarchitecture. Responsibilities include creating test benches, driving bug analysis, and participating in design reviews, with a focus on RISC-V architecture.
Top Skills: BashCC++PythonShellSystemverilog
Junior
Hardware • Automation
The Hardware Design Engineer will define and implement microarchitectures for RISC-V processors, collaborate with teams on verification, optimize designs for performance, and utilize tools for synthesis and automation.
Top Skills: PythonRisc-VShellSystemverilogTclVerilog
Codasip Logo
Codasip

Principal Verification Engineer

Yesterday
2 Locations
Senior level
Senior level
Hardware • Automation
The Principal Verification Engineer will verify advanced RISC-V processors, develop verification solutions, collaborate with teams, define verification strategies, run simulations, and mentor junior engineers. Responsibilities include ownership of verification activities and crafting automated flows for debugging and root cause analysis.
Top Skills: C++GoPythonRustSystemverilog
Codasip Logo
Codasip

Formal Verification Engineer

Yesterday
4 Locations
Mid level
Mid level
Hardware • Automation
The Formal Verification Engineer will be responsible for applying formal verification techniques to Codasip processors, reviewing FV test plans, developing tools, and ensuring the quality of RISC-V processor deliverables. Responsibilities include enabling formal verification users and contributing to innovative processor designs.
Top Skills: PythonSystemverilogVerilogVhdl
Codasip Logo
Codasip

CPU Design Engineer

Yesterday
2 Locations
Mid level
Mid level
Hardware • Automation
The CPU Design Engineer at Codasip will innovate and develop high-performance CPU cores based on RISC-V architecture using Codasip Studio and CodAL. Responsibilities include customizing IP cores, participating in design verification, and reporting results at international venues, requiring hands-on experience in processor development and background in digital design and embedded systems.
Top Skills: AssemblyBashCC++MatlabPythonRisc-VSystemcSystemverilogVerilogVhdl
All Filters
Date Posted
Job Category
Experience
Industry
Company Name
Company Size

Sign up now Access later

Create Free Account