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Yesterday
Santa Clara, CA, USA
148 Employees
Mid level
148 Employees
Mid level
Big Data • Information Technology
The Senior Design Verification Engineer will be responsible for the full verification lifecycle of complex ASICs, including planning, test writing, debugging, and coverage closure. The role requires working with software and validation teams to execute test plans on emulation platforms while employing both directed and constrained random verification techniques.
Yesterday
Santa Clara, CA, USA
148 Employees
170K-250K Annually
Senior level
148 Employees
170K-250K Annually
Senior level
Big Data • Information Technology
The Principal Signal/Power Integrity Engineer will execute signal integrity (SI) planning, design, modeling, simulation, and lab validation for high-speed connectivity products. Responsibilities include formulating validation plans, designing experiments to identify root causes of issues, and collaborating with internal stakeholders to ensure system robustness and compliance.
Yesterday
Santa Clara, CA, USA
148 Employees
Expert/Leader
148 Employees
Expert/Leader
Big Data • Information Technology
Lead the content marketing strategy at Astera Labs by building a robust pipeline of engaging content for multiple product lines, managing and mentoring the content team, and implementing SEO techniques. Work with cross-functional teams to create fresh content across various platforms, track engagement levels, and produce performance reports to drive improvement in content effectiveness.
Yesterday
Santa Clara, CA, USA
148 Employees
Expert/Leader
148 Employees
Expert/Leader
Big Data • Information Technology
The Sr. Principal Technologist will drive the architecture and development of COSMOS software solutions, engage with customers, influence product features, and provide innovative solutions for hyperscale data centers, leveraging extensive expertise in software and system management.
Yesterday
Santa Clara, CA, USA
148 Employees
120K-190K Annually
Senior level
148 Employees
120K-190K Annually
Senior level
Big Data • Information Technology
The Senior Firmware Verification Engineer will verify firmware and microcontroller subsystems for SoC and system products using both white-box and black-box testing. Responsibilities include developing test plans, reviewing code, collaborating with development teams on HW-SW interfaces, creating automated test scripts in Python, and ensuring comprehensive testing of the product lifecycle.
Yesterday
Santa Clara, CA, USA
148 Employees
160K-240K Annually
Senior level
148 Employees
160K-240K Annually
Senior level
Big Data • Information Technology
The Principal Product Manager will lead product definition and launches for AI semiconductor solutions, driving customer engagement, go-to-market strategies, and collaboration with cross-functional teams to ensure product success and growth.
Yesterday
Santa Clara, CA, USA
148 Employees
140K-200K Annually
Senior level
148 Employees
140K-200K Annually
Senior level
Big Data • Information Technology
As a Senior Product Manager at Astera Labs, you will manage AI semiconductor solutions for data center applications, drive product definition, lead engineering interactions, and develop go-to-market strategies.
Yesterday
Santa Clara, CA, USA
148 Employees
140K-200K Annually
Senior level
148 Employees
140K-200K Annually
Senior level
Big Data • Information Technology
The QA Firmware Engineer will validate COSMOS Firmware and SDKs for Astera Labs' SoCs and systems products, develop test plans, procedures, and execute tests, and analyze test results. They will work closely with development to ensure implementation quality.
Yesterday
Santa Clara, CA, USA
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
The Senior Firmware Engineer at Astera Labs is responsible for architecting and developing firmware and microcontroller subsystems for SoC and systems products. This role focuses on developing key features, collaborating with logic designers, and ensuring firmware meets customer demands while managing multiple tasks effectively.
Yesterday
Santa Clara, CA, USA
148 Employees
140K-200K Annually
Senior level
148 Employees
140K-200K Annually
Senior level
Big Data • Information Technology
The Senior Digital Design Engineer will develop micro-architecture and front-end circuit design including RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. Responsibilities include hands-on design work and ownership of designs from architecture to production.
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