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Lead physical design and implementation of SOC devices in the networking market, addressing timing and congestion issues. Responsibilities include all aspects of physical chip development from RTL to GDS, involving synthesis, place and route, and physical verification.

The Senior ASIC Design Engineer will develop logic for high-performance multi-GPU/CPU/DPU systems, focusing on micro-architecture, RTL coding, timing closure, and power optimization. This includes working with various industry protocols and collaborating with teams to deliver high-quality IP.

The Senior ASIC Timing Engineer will drive the physical design and timing for high-frequency and low-power DPUs and SoCs. Responsibilities include analyzing design constraints, optimizing synthesis parameters, and implementing both frontend and backend processes from RTL to GDS2. The role requires collaboration on timing convergence and design closure in deep-submicron processes, utilizing advanced timing tools and scripting languages.