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Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Expert/Leader
8,216 Employees
Expert/Leader
Cloud • Hardware • Software • Semiconductor
The Sr. Principal Software Engineer will provide R&D support for customer-related issues, analyzing and fixing problems, as well as developing new features. The role requires significant problem-solving and innovative research in the EDA domain, with opportunities for mentoring in software engineering skills.
Yesterday
Edinburgh, Midlothian, Scotland, GBR
8,216 Employees
Expert/Leader
8,216 Employees
Expert/Leader
Cloud • Hardware • Software • Semiconductor
The Sr Principal Digital Verification Engineer will work on the architecture and management of verification environments for complex IP, develop self-checking regressions and functional coverage, and create automated regression environments while collaborating closely with design engineers.
Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Senior Principal Design Engineer at Cadence is responsible for developing software for embedded processors and emulation platforms, focusing on efficient algorithms and data structures. The role demands strong programming skills in C/C++ and experience in firmware programming. Additionally, the engineer will collaborate with teams and customers while potentially engaging in international travel. A solid foundation in computer architecture and understanding of Neural Networks is beneficial.
Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
As a Senior Account Technical Executive I, you will manage strategic accounts at Cadence, maximizing the value of their technology solutions, grow product adoption, and drive technical sales engagements. You will develop strategies, build relationships with stakeholders, and coordinate with internal teams to meet customer challenges and sales targets.
Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Principal Design Engineer will lead design verification projects, ensuring complex designs are verified from concept to closure. Key responsibilities include environment planning, test plan generation, and developing functional verification environments using System Verilog and UVM.
Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Mid level
8,216 Employees
Mid level
Cloud • Hardware • Software • Semiconductor
As a Principal Design Engineer, you will be responsible for the verification of Serial and Interface Design IPs, utilizing UVM testbench development for efficient verification and participating in formal verification and emulation qualification. The role requires strong analytical, problem-solving skills, and effective communication capabilities.
Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Sr Design Engineering Architect role involves RTL design for PCIe Architect with responsibilities in creating and supporting the RTL of PCIe/CXL/IDE/UALink IP solutions. The role requires significant expertise in various subsystems and ensures design compliance with verification guidelines.
Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Mid level
8,216 Employees
Mid level
Cloud • Hardware • Software • Semiconductor
As a Lead Design Engineer at Cadence, you will work on embedded processors, implement high-performance algorithms, and write/debug software for emulation platforms. You'll collaborate with diverse teams and customers to address issues while leveraging knowledge in Neural Networks and Deep Learning.
Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Principal Design Engineer will lead major blocks of Memory PHY layout design, engaging in hands-on critical analog and high-speed layout blocks. Responsibilities include coordinating with circuit leads, layout contractors, and team members, as well as participating in layout reviews.
Yesterday
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Lead Software Engineer at Cadence will enhance software development for the Protium P&R tool, focusing on improving quality of results (QoR) and performance timing while collaborating with users to deploy new features. Candidates must have a strong background in software development and CS fundamentals.
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