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The role involves leading the design of analog blocks for advanced mixed-signal circuits, writing detailed specifications, collaborating with architects and designers, verifying designs to ensure silicon quality, and managing vendor relationships.

The UPF Engineer will develop and validate power intent definitions for SOC designs, focusing on power efficiency. Responsibilities include overseeing the entire RTL to GDS flow, ensuring power intent coverage, and collaborating with various teams to optimize power-aware simulations.

Develop PDV methodology and infrastructure for large SoCs, drive convergence at full chip level, work with internal and external design teams, manage team of engineers for PDV convergence.

Seeking a Senior Memory Design Engineer with 8-10 years of experience in custom circuit design, SRAM memories, Register file memories, SRAM compilers, and low power design techniques. Responsibilities include driving the design and development of custom circuits, working with microarchitecture team, conducting PPA analysis, equivalence checking, collaborating with CPU and SoC teams, and interacting with technology and CAD teams.

The role involves designing and implementing optimized communication libraries for Deep Learning systems, collaborating with hardware and software teams to ensure data synchronization across AI accelerators, and optimizing algorithms for distributed computing applications.

Positions are open for a full-time SOC Emulation Engineer to work on developing Emulation and FPGA-based prototyping systems for SOC projects. Responsibilities include creating and supporting emulation models, driving SOC bringup, developing compile and runtime flows, working with tool vendors, and contributing to methodology and automation improvements.