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The Senior Memory Design Engineer will develop SRAM memories and custom circuits, ensuring high performance and low power design through collaboration and innovative problem-solving.

The DFT Engineer role involves designing DFT strategies, defining test structures, and ensuring designs meet DFT requirements while collaborating with various teams.

The Memory Subsystem Architect specifies memory subsystem architecture, collaborates with internal teams, and contributes to industry standards while ensuring performance and power requirements are met.