Analog Mixed Signal Design

Posted Yesterday
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Hsinchu County
Hybrid
Senior level
Software
The Role
As an Analog Engineer, you will lead the design of advanced mixed-signal circuits, writing specifications and collaborating with architecture and verification engineers. Responsibilities include behavioral modeling and supporting integration and characterization efforts. You will ensure high-quality silicon through effective communication with team members and external vendors.
Summary Generated by Built In

Join a well funded startup as an analog engineer leading the designs for droop sensing, clocking, PLL, LDO, On-die VRs and PMICs using latest finfet technology nodes. Our mission is to reimagine silicon and disrupt the high performance computing platforms with the RiscV based chiplet designs. 

Responsibilities

  • Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
  • Write detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.
  • Work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon.
  • Lead development of analog blocks in collaboration with external vendors and lead integration, test plan and characterization efforts.

Requirements

  • Strong track record of architect, develop, verification and validation of complete silicon IPs
  • Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters
  • In-depth knowledge and good understanding of analog design techniques.
  • Experience in digital integration of analog IPs with chip level integration team
  • Experience in developing behavior modeling a plus
  • Experience IP design management or vendor management a plus
  • Strong device physics knowledge as it applies to analog IC design
  • Hand-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
  • Experience in working with production test engineers to produce test plans and design for testability details
  • Excellent communication skills
  • Team player with an ability to encourage team members

Education & Experience

  • MS (preferred in EE) plus 8 years
  • PhD (preferred in EE) plus 5 years
The Company
HQ: Mountain View, CA
287 Employees
On-site Workplace
Year Founded: 2021

What We Do

Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise

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