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RTL Design Engineer

Reposted 19 Days Ago
Cupertino, CA, USA
2K-2K
Senior level
2K-2K
Senior level
Artificial Intelligence • Hardware • Software
The RTL Design Engineer will develop verification strategies for ASIC designs, focusing on machine learning and digital logic, requiring at least 5 years of experience.
Top Skills: Asic DesignDigital LogicPythonRtl DesignVerification Tools
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