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As a Senior IC Layout Mask Designer, you will lead layout activity for high performance analog cores and establish layout procedures. Responsibilities include working with industry-standard EDA tools, layout for high performance analog blocks, and managing layout team activities.

The Senior DFT Engineer will drive DFT flows for digital designs, collaborating with RTL and physical design teams to enhance testability. Responsibilities include defining DFT strategies, creating test structures and vectors, and resolving design issues related to DFT. The role requires hands-on experience with test generation tools and a strong understanding of digital ASIC design.

The Senior Digital/Mixed-Signal IC Design Engineer will develop and verify digital controllers for data converters, engage in behavioral modeling, provide customer support, and assist with synthesis and place-and-route processes, focusing on high-performance analog-to-digital and digital-to-analog converters.