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The Memory Subsystem Architect specifies memory subsystem architecture, collaborates with internal teams, and contributes to industry standards while ensuring performance and power requirements are met.

The Senior Power-Management Architect will model and optimize power/performance features on Risc-V designs, collaborating with various teams to enhance product quality.

The Senior Power-Management Architect will model and optimize performance features, define power management features, and collaborate with various teams on Risc-V architecture.

The role involves modeling and optimizing power/performance features for Risc-V architecture, collaborating with engineering teams, and integrating firmware.

As a Senior Power-Management Architect, you will model and optimize power/performance features, define management features, and collaborate with teams for implementation and analysis.

The role involves verifying DDR and HBM memory subsystems by developing test plans, integrating VIPs, and collaborating with design teams and vendors.

As a memory subsystem design verification engineer, you'll verify DDR and HBM memory designs, develop test plans, and work on emulation support.