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The Silicon Physical Design Verification Manager will develop PDV methodology and infrastructure for verifying large SoCs, ensuring quality integration across design teams and driving convergence at both full chip and sub-block levels, while managing a team of engineers to meet project milestones.

Seeking a Senior Memory Design Engineer with 10 years of custom circuit design experience to drive the design and development of SRAM, register file, and custom cells for high performance and low power designs. Responsibilities include working with microarchitecture team, conducting PPA analysis, design equivalence checking, collaborating with CPU and SoC physical design teams, and interacting with technology and CAD teams.

Responsible for internal interconnect architecture specification and performance optimization. Collaborate with Silicon team members and industry consortiums. Develop, assess, and refine architecture to meet power, performance, and timing goals.