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The Tech Lead Firmware Engineer will design and develop Firmware to enable DDR technologies for innovative products at Astera Labs, focusing on CXL memory solutions. Responsibilities include debugging DDR-related issues and potentially collaborating with cross-functional teams on DDR memory interfaces.
As a Senior Software/Firmware Engineer at Astera Labs, you will architect and develop firmware and microcontroller subsystems for SoC and systems products, ensuring the integration of differentiated features and customer interaction. You should have a strong technical background in embedded software, firmware development, and relevant communication protocols, focusing on the needs of the customer while coordinating with hardware teams.
As an Ecosystem Manager, you will oversee interactions with industry partners for high-speed communication protocols. Your role includes strategic planning, ecosystem enablement, and managing marketing initiatives across teams.
The Senior Product Applications Engineering Manager will lead a team providing technical support for semiconductor products, address customer design challenges, generate product collateral, and collaborate with internal teams for product innovation. This role requires managing customer relationships and hands-on lab work to troubleshoot high-speed interface issues.
The Principal Product Manager at Astera Labs will lead the product definition and launch of AI semiconductor solutions, manage customer relationships, and develop go-to-market strategies. This role involves collaboration with cross-functional teams to ensure successful product development and delivery, while also identifying new markets and influencing senior leadership.
As a Senior Field Applications Engineer, you will lead a team to act as trusted technical advisors for cloud service providers. Your role involves designing solutions using Astera Labs’ connectivity products, proposing solutions based on customer needs, and collaborating with engineering to drive product innovation.
The Senior Physical Design Engineer will develop and support complex SoC/silicon products for various applications. Responsibilities include using physical design tools, driving designs from architecture to production, collaborating with IP vendors, and ensuring timing closure and formal verification.
As a Senior DFT Engineer at Astera Labs, you will work on developing next-generation connectivity products, engaging in all product lifecycle stages. Collaboration with various teams is essential, focusing on chip design and DFT techniques such as ATPG and JTAG while ensuring quality through testing and analysis.
The Senior Design Verification Engineer will develop and execute verification plans, write and execute test sequences, collaborate with RTL designers, and analyze coverage data. Responsibilities include using coding expertise for functional verification and creating VIP abstraction layers for simplified verification processes.
As a Principal Physical Design Engineer, you will lead complex SoC/silicon product designs for Server, Storage, and Networking applications. You will be responsible for full chip or block level ownership, synthesis, timing closure, and verification, while utilizing backend tools and methodologies.
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