Lead EDA tools and engineering workflow development for multimodal generative AI inference acceleration products at Recogni. Drive optimization, implementation, and exploration of new EDA tools for ASIC chip design process. Collaborate with ASIC team members to enhance workflows and EDA needs.

Responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC. Works closely with design verification engineers and collaborates with the physical design team.