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The Senior Manager will lead the Static Timing Analysis team, developing advanced methodologies, managing project timelines, and ensuring the timing performance of semiconductor designs. Responsibilities include mentoring engineers, collaborating across teams, automating timing analysis processes, and presenting detailed reports to stakeholders, while fostering a culture of innovation and improvement.

The role involves leading the STA function for ASIC designs, developing methodologies for timing closure, and mentoring engineers. The candidate will conduct detailed timing analyses, collaborate with various teams, and troubleshoot complex timing issues, ensuring project milestones are met.

The Staff Engineer, Firmware Engineering at Western Digital is responsible for designing, implementing, and debugging firmware for next-gen storage devices like SD, USB, and SATA. This role involves working in an Agile environment and dealing with complex embedded systems while collaborating with teams across cultures.