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As a Lead Support Application Engineer at Cadence in Bangalore/Noida, you will provide technical support for IC level Power System analysis products, work closely with customers to debug complex issues, and guide them with implementing software in their design methodologies. You will have opportunities for technical knowledge acquisition, exposure to industry design practices, and contribute to key technology solutions. Join a diverse team passionate about innovation and technology.
As a Principal Application Engineer at Cadence, you will provide technical consultation for digital & sign-off domain products to worldwide customers, debug complex issues, guide implementation of software, and contribute to product improvement initiatives.
Cadence is hiring a Memory Design Engineer with 15-25 years of experience to work in their Memory IP team in Hyderabad. The responsibilities include circuit design, simulation, verification, and silicon bring-up for memory design blocks. Proficiency in Cadence, Mentor Graphics, and Synopsys tools is required, along with good technical communication and teamwork skills.
Work with the Cadence global IC design team to develop semiconductor IP for top electronic product companies, ensuring continuous quality improvement and adherence to quality procedures.
Lead Design Engineer responsible for creating and maintaining functional verification environments, defining verification strategies, and collaborating with cross-functional teams. Requires expertise in Verilog, SystemVerilog, UVM methodology, RTL, and various verification domain skills. Desirable skills include power-aware RTL, formal verification, gate-level simulations, and exposure to automotive IP verification.
Join a growing team at Cadence as a Sr Principal Design Engineer, responsible for leading the Design for Test activities for next-gen SoCs. Define DFT architecture, implement verification logic, collaborate with teams, and work on silicon bring up. Ideal candidate has 8-15+ years of experience with key DFT concepts and working knowledge of Verilog coding
Immediate opening for a Design Engineering Manager at Cadence Design Systems in Bangalore. Responsibilities include leading pre and post silicon Physical Layer Electrical Validation efforts. Looking for candidates with 6-10 years of experience in the field and expertise in High Speed SERDES protocols like PCIe, USB, DP, ethernet, and more.
The Sr. Principal Software Engineer at Cadence will be responsible for UI/UX development in React.js, optimization of website performance, integration with backend services, creating data visualizations, and backend infrastructure development.
Looking for a Senior Principal RTL Design Engineer with 12+ years of ASIC design experience. Proficiency in Verilog coding, RTL design, and various interface protocols. Must have knowledge of RTL checks and synthesis flow.
Cadence is looking for a passionate Layout Design professional with 2-14 years of experience in Analog Layout and SerDes IP. The role involves working on cutting edge FinFET technologies and collaborating with Tier-1 customers. Responsibilities include hands-on layout experience in various analog IPs, knowledge of layout effects on circuits, understanding of DSM technology, and communication skills. Scripting and automation experience is a plus.
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