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Lead Solutions Engineer responsible for developing verification strategies and test plans, writing tests, creating verification environments, and working with AMBA protocols and various other protocols. Must have strong communication and organizational skills.

Lead Analog Layout Design Engineer responsible for designing high speed SERDES products at data rates exceeding 112 Gbps on leading edge technology nodes. Collaborates with circuit designers, mentors junior engineers, and works with global teams. Requires 4 years of experience in CMOS SERDES or high-speed I/O IC layout design.

The Senior Product Marketing Manager will lead product marketing for Cadence's Tensilica processor IP, focusing on market success through customer collaboration and competitive positioning. Responsibilities include defining product requirements, coordinating product enhancements, and driving marketing activities while working closely with engineering and sales teams.

The Sr Systems Engineer at Cadence will manage IT user requirements through Jira tickets, provision hardware, assist with general IT infrastructure support, and ensure high uptime of IT services. Responsibilities also include communication with partners for infrastructure deployment and providing support during scheduled maintenance.

Looking for a Senior Technical Project Manager to coordinate R&D Development Projects and Key Customer Engagements within the Design IP Group. Must have 15 years of experience in mixed-signal design and end-to-end flow.

Architect solutions and design RTL for DDR memory controllers in a highly configurable environment. Collaborate with cross-functional teams to develop high-speed circuits and low-power features. Lead technical teams to advance product quality and efficiency. Essential qualifications include experience in Verilog RTL Design, Metric Driven Verification, and Front-end design tools.

As a Genus R&D Software Engineer, you will design, develop, troubleshoot, and support the Genus synthesis product. You will work on innovative technologies to enhance microchip design by optimizing algorithms for performance and efficiency. Your contributions will significantly impact the quality of results in circuit synthesis.