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The ASIC Design Engineer is tasked with developing and enhancing timing analysis/signoff workflows, managing chip level integration, physically partitioning and floor planning, and optimizing designs. This role includes creating custom timing scripts for clock skew analysis and engaging in design optimization tasks to ensure effective design implementation from micro-architecture to tape-out.

Design and implement SoCs, defining micro-architectures and developing RTL while collaborating with verification teams. Responsibilities include owning silicon bring-up, mentoring junior engineers, and ensuring accurate verification and implementation of features.

As an ASIC Engineer at NVIDIA, you will own the micro-architecture and RTL development of PCI Express Controllers, collaborate with design teams, and ensure correct feature implementation through verification and post-silicon debug. You will work closely with multiple teams to meet performance, power, and area requirements.

This role involves system-level performance analysis of complex GPUs and SoCs, development of performance models and test suits, and collaboration with architecture teams to optimize performance, area, and power. You'll also develop infrastructure for early performance analysis and improve methodologies for data representation.

The Senior Systems Engineer will enhance and scale a cloud compute platform for Autonomous Vehicles, design scalable services, support multiple teams, and ensure effective operations and user support, all while leveraging state-of-the-art technologies and collaboration skills.

Profile and analyze AI workloads on large GPUs and CPUs scale clusters for distributed Deep Learning LLM training with a focus on high-performance networking. Develop performance analysis tools and methodologies to understand performance expectations, limitations, and bottlenecks. Collaborate with cross-functional teams to provide performance analysis insights.

As a Senior ASIC Design Engineer, you will implement and deliver high-performance RTL designs, analyze architectural trade-offs, and collaborate with various teams. You will work with a range of IPs and support silicon validation activities, utilizing your expertise in ASIC design and RTL development.