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The Senior Mask Layout Design Engineer at NVIDIA will perform physical layout for mixed-signal functions using Cadence tools and engage in floor planning and verification. They will collaborate with ASIC and mixed-signal engineers for VLSI product integration, leveraging their expertise in sub-micron CMOS technologies and layout concepts.

The Senior HPC Systems Engineer will design and implement performance practices for large-scale AI and datacenter applications, aid in customer deployments, engage with software and firmware teams, and optimize datacenter product designs to enhance GPU-accelerated computing performance.

The Senior AI Software Engineer will develop the GenAI open-source NeMo framework and Megatron Core. Responsibilities include solving large-scale AI training challenges, performance tuning, and collaborating on optimizations and new model features with internal partners and the open source community.

As a Senior C++ Software Engineer at NVIDIA, you will develop efficient software to automate chip design workflows, optimize processes for design teams, and collaborate with engineers worldwide. This role involves leveraging modern software development practices and exploring AI advancements in CAD tools.

As a Senior DFT Methodology Engineer at NVIDIA, you will work on next-generation test architectures and develop In-System Test methodologies. Responsibilities include implementing test access mechanisms, mentoring junior engineers, and utilizing DFT techniques such as ATPG and fault simulation on complex semiconductor chips.

The System Software Engineer will design and develop frameworks and tools for GPU workloads, collaborate with GPU architects, and improve workflows for chip modelers. The role involves creating GPU stimulus analysis tools and ensuring infrastructure is effective throughout the chip lifecycle, heavily relying on C++ programming expertise and knowledge of graphics APIs.

As an ASIC Verification Engineer at NVIDIA, you'll develop and implement verification methodologies for DFT IP at unit and system levels, create test benches, and collaborate with various teams. Your expertise in SystemVerilog and UVM will be vital in building reusable verification components and achieving verification closure.