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Lead the integration of firmware into new hardware, resolving high-impact issues while mentoring a team of system integration engineers. Collaborate with cross-functional teams to ensure seamless integration of NVIDIA products, leveraging strong problem-solving and communication skills.

The Senior ASIC Timing Engineer will drive the physical design and timing for high-frequency and low-power DPUs and SoCs. Responsibilities include analyzing design constraints, optimizing synthesis parameters, and implementing both frontend and backend processes from RTL to GDS2. The role requires collaboration on timing convergence and design closure in deep-submicron processes, utilizing advanced timing tools and scripting languages.

As a Senior Site Reliability Engineer at NVIDIA, you will design and implement HPC storage solutions, automate management of infrastructure environments, and ensure optimal performance of storage systems. You will collaborate with engineering teams to align infrastructure with needs, document best practices, and foster innovation in AI and computing.