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The role involves mixed-signal and analog circuit design for high-speed memory I/O interfaces, working on challenges associated with circuit designs in the latest CMOS FinFET processes. The engineer will take designs through productization while collaborating with multi-functional teams to optimize designs and ensure system-level integrity.

The Senior Mask Layout Design Engineer will lead IC physical layout for mixed-signal functions, collaborating with various engineers to customize designs for VLSI products. Responsibilities include floor planning, optimizing layouts, verifying designs against rules, and providing post-silicon debugging support. The role emphasizes expertise in analog circuit layout and proficiency in EDA tools.

As a Senior DL Algorithms Engineer, you will optimize Deep Learning workloads for NVIDIA, analyzing and debugging performance of models, delivering optimized LLM inference solutions, and collaborating across teams to enhance AI services. A strong background in deep learning, programming in C++, and Python, along with a PhD in a relevant field, is required.