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The role involves developing PDN & PV methodologies for SoC designs, collaborating with teams, managing requirements, and evaluating tool offerings.

Develop digital sections for memory data buffer chips, lead design efforts, mentor engineers, and ensure high standards in ASIC design processes.

The engineer will translate RF PHY specifications into architectures, develop RF solutions, collaborate with teams, and lead system validation efforts.

Responsible for managing hardware development of SoC/MCU projects, ensuring timely delivery and quality while leading cross-functional teams and processes.

The Staff RF PHY System Engineer will design RFIC architectures, analyze systems, develop specifications, and validate RF systems in collaboration with multidisciplinary teams.

The Principal Engineer will lead collaboration on CDC/RDC solutions, evaluate EDA tools, and drive the adoption of new methodologies across the organization.

The Sr Staff Digital Engineer will lead the design of digital functional blocks, manage RTL design, and ensure compliance with specifications for power management ICs, while also handling silicon debug and documentation.