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The Sr Staff Engineer will design and develop the PCIe/IO subsystem for a high-performance CPU SoC, create specifications, implement reusable components, ensure integration and performance optimization, and collaborate with various teams for high-quality delivery.

The RISC-V Program Manager will oversee the development of chip architectures for CPU server and machine learning processors, ensuring project schedules are met and collaborating with cross-functional teams to deliver solutions that meet customer needs.

The Digital DV Engineer at Tenstorrent will be responsible for the verification of digital IP and SOC logic, using advanced methodologies. Responsibilities include creating test plans, writing testbenches, reviewing verification metrics, and conducting performance and power validation of the products.

As a Staff Engineer for RTL Design at Tenstorrent, you will implement digital IPs for CPUs and AI/ML chiplets, focusing on RTL coding in Verilog and microarchitecture of security subsystems. You will collaborate with design and validation teams, improve design performance, and debug across various hierarchies.

The Staff Customer Solutions Engineer role involves engaging with OEM/ODM customers to assist in the design development of data center systems using Tenstorrent products. Responsibilities include addressing customer requirements, leading technical discussions, developing innovative architectures, training partners, and collaborating with various teams to resolve design issues and support customer projects.

The SOC Physical Design Lead is responsible for managing floor planning and block-level physical implementation for high-performance designs. This includes overseeing SoC integration, directing layout verification, and collaborating with architecture, RTL, and packaging teams while driving methodology and tool enhancements.

The SOC Architect will lead the design and standardization of modular chiplet architectures, develop interconnect protocols, and establish open architecture standards. Responsibilities include overseeing collaborative efforts with industry bodies, optimizing performance and integration, and mentoring engineering teams on chiplet design and verification.