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Lead design efforts for high-speed low-noise clocking circuitry, including fractional-N PLLs and clock distribution networks. Collaborate and supervise team members.

Lead design efforts of high-speed low-noise clocking circuitry, including fractional-N PLLs and clock distribution networks for efficient high-speed transmission.

The Staff Engineer will design custom analog circuits, optimize layout, and ensure power integrity while collaborating with circuit designers for efficient high-speed analog transmission solutions.