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Rivos

Memory Controller Verification

25 Days Ago
Hybrid
Austin, TX, USA
Mid level
Mid level
Software
The role involves verifying DDR and HBM memory subsystems by developing test plans, integrating VIPs, and collaborating with design teams and vendors.
Top Skills: Systemverilog,Uvm
Rivos Logo
Rivos

Memory Controller Verification

25 Days Ago
Hybrid
Santa Clara, CA, USA
Mid level
Mid level
Software
As a memory subsystem design verification engineer, you'll verify DDR and HBM memory designs, develop test plans, and work on emulation support.
Top Skills: DdrHbmSystemverilogUvm
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