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The Staff Formal Data-Path Verification Engineer will identify blocks for Data-Path Formal Verification, set up and debug verification processes, guide team members, and maintain assertion libraries. They will apply FV techniques and develop scripts for automation.

Implement and validate DFT structures on various processor core IP subsystems, contribute to DFT implementation flow development, meet performance, power, and area goals on DFT-inserted CPU designs.

The Principal Verification Engineer at SiFive will ensure the fidelity of new RISC-V based CPU IPs and other related components. Responsibilities include understanding system components, creating verification strategies, participating in design phases, and ensuring verification quality through metrics. The role involves solving verification challenges of memory subsystems and cache verification, requiring extensive experience in functional verification and deep knowledge of computer architecture.

The Sr. Staff Verification Engineer will verify the functionality of RISC-V based CPU IPs, ensuring design fidelity through test planning, execution, and coverage metrics. Responsibilities include adopting advanced methodologies and collaborating on high-performance Out-of-Order Core components for diverse applications such as 5G and IoT.

The Power Engineer will focus on power simulation and modeling for ASIC designs, conduct power analysis and optimization, and write scripts using Python, Perl, or Tcl. The role requires strong problem-solving skills and a collaborative approach in a dynamic environment.

The Sr. Technical Program Manager will coordinate and lead cross-functional teams throughout the product life cycle, focusing on CPU core design and related tools. Responsibilities include developing project plans, tracking program execution, participating in technical discussions, and enhancing program management processes. The role requires excellent communication and project management skills, alongside experience with CPU technology and related software.

Develop and enhance debugging and profiling tools for SiFive RISC-V processors. Responsibilities include improving command line and IDE tools, engaging with teams for new feature refinement, implementing best software development practices, and providing customer support as needed.