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13 Days Ago
San Jose, CA, USA
2,298 Employees
177K-283K Annually
Expert/Leader
2,298 Employees
177K-283K Annually
Expert/Leader
Semiconductor
The Senior Manager for ASIC Design Enablement is responsible for managing the end-to-end implementation of cutting-edge ASIC designs. This includes collaborating with internal teams and clients, overseeing chip-level floorplanning, budgeting, chiplet integration, and ensuring successful design implementation through various verification processes.
16 Days Ago
San Jose, CA, USA
2,298 Employees
229K-401K Annually
Expert/Leader
2,298 Employees
229K-401K Annually
Expert/Leader
Semiconductor
In this role, you will research and optimize logic technology paths, develop architecture for standard cells, assess new device architectures, and analyze design rules to improve technology performance while collaborating with multiple teams and external vendors.
17 Days Ago
San Jose, CA, USA
2,298 Employees
162K-258K Annually
Senior level
2,298 Employees
162K-258K Annually
Senior level
Semiconductor
The Senior Manager, Memory Sales will manage a strategic account in memory and AI/datacenter markets, enhance customer engagement, and collaborate with internal teams to deliver tailored solutions, driven by market expertise and data-driven strategies.
17 Days Ago
San Jose, CA, USA
2,298 Employees
108K-218K Annually
2,298 Employees
108K-218K Annually
Not Specified
Semiconductor
The Manager, NAND/SSD Field Application Engineer will be responsible for managing technical accounts for NAND solutions and maximizing sales contribution.
17 Days Ago
San Jose, CA, USA
2,298 Employees
153K-237K Annually
Senior level
2,298 Employees
153K-237K Annually
Senior level
Semiconductor
Contribute to high-performance web-based tools, design and implement APIs, manage databases, automate build and deployment processes, analyze performance, and stay updated on web development advancements. Communicate with stakeholders to ensure project delivery within budget and timelines.
17 Days Ago
San Jose, CA, USA
2,298 Employees
229K-401K Annually
Expert/Leader
2,298 Employees
229K-401K Annually
Expert/Leader
Semiconductor
The role involves designing and implementing ML compilers for deep learning applications, optimizing them for hardware, collaborating with hardware architects, and staying current with advancements in ML compiler technology. The position emphasizes cross-functional teamwork and technical support.
17 Days Ago
San Jose, CA, USA
2,298 Employees
191K-305K Annually
Expert/Leader
2,298 Employees
191K-305K Annually
Expert/Leader
Semiconductor
In this role, you will oversee the Workplace Solutions Group, managing capital projects and daily operations at the San Jose headquarters. Responsibilities include budget management, project oversight, team leadership, improving employee experiences, and ensuring compliance with regulations. You will collaborate with various departments and present to senior leadership.
17 Days Ago
San Jose, CA, USA
2,298 Employees
161K-257K Annually
Senior level
2,298 Employees
161K-257K Annually
Senior level
Semiconductor
The Senior Manager of Workplace Operations oversees facility operations, ensuring performance meets objectives while managing technical operations, occupant relations, and financial results. Responsibilities include evaluating facility performance, assisting in long-range strategy, managing compliance with lease provisions, and providing leadership for team development and service delivery excellence.
17 Days Ago
Folsom, CA, USA
2,298 Employees
139K-215K Annually
Senior level
2,298 Employees
139K-215K Annually
Senior level
Semiconductor
The Staff SoC Design Engineer will enhance storage capabilities by developing and optimizing prototype SSD controllers, integrating third-party IP for the HBM memory subsystem, and working closely with verification and physical design teams to ensure timing and functional coverage.
17 Days Ago
Folsom, CA, USA
2,298 Employees
139K-215K Annually
Senior level
2,298 Employees
139K-215K Annually
Senior level
Semiconductor
Develop verification environments for HBM memory subsystems in SoC design. Create verification plans, generate test cases, and develop coverage models. Collaborate with designers and architects for sign-off on verification requirements while ensuring a successful verification flow and tool usage.
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