As a Senior/Principal Embedded Software Engineer, you will design and implement embedded software for hardware platforms, work with customers to transition to RISC-V CPUs, and mentor junior team members.

The role involves verifying new Codasip IP designs, contributing to system-level verification using SystemVerilog and UVM test benches, and collaborating with a distributed team.

The Hardware Design Engineer at Codasip will contribute to the development of RISC-V processors, focusing on microarchitecture definition, block specification, and component design. Responsibilities include designing solutions for process automation, working closely with verification teams, and ensuring design meets performance targets.

As a Senior Hardware Engineer at Codasip, you will be responsible for the microarchitecture definition and implementation of RISC-V processors, work on design synthesis, collaborate with verification teams, and produce technical documentation. This role involves leading complex design projects in a dynamic international environment.

The Senior Field Application Engineer will provide pre and post-sales support, engage with customers technically, and build strong relationships while collaborating with engineering and sales teams.

Lead Chiplet development by architecting, designing, and verifying high-performance silicon chiplets, coordinate with outsource partners, and ensure best practices in design processes.

As a CPU Emulation Engineer, you will develop and integrate support for custom CPU cores and interfaces, and work on emulation tools and technologies.

As a Verification Engineer, you will verify RISC-V processors, create pre-silicon verification environments, and automate testing processes while collaborating with distributed teams.

As a Hardware Design Intern, you will develop next-gen RISC-V processor cores, work on design and verification, and utilize EDA tools.

The Hardware Verification Intern will ensure quality in modern RISC-V processors, gaining hands-on experience in verification methodologies and collaborating with experienced engineers.

The Verification Engineer will verify RISC-V processors, develop verification solutions, collaborate with teams, define strategies, and track metrics.

The intern will develop formal verification IP for Codasip RISC-V CPUs by analyzing and implementing new methodologies to improve verification performance.

As a Compiler Engineer, you will customize and optimize LLVM for RISC-V CPU cores, enhance compiler features, support embedded software teams, and contribute to novel computing architectures.

As a Senior LLVM Compiler Engineer, you will customize LLVM compilers, optimize performance for embedded CPU cores, and support hardware design teams with compiler expertise.

The Formal Verification Engineer is responsible for applying formal verification techniques to improve the quality of RISC-V processors, contributing to tool development, and enabling the use of advanced methodologies in verification processes.

The Hardware Verification Engineer will create verification environments for RISC-V processors, design automated tests and continuously improve technologies.

The C++ Developer will work on CodAL team focusing on compiler development, code maintenance, unit testing, and performance optimization for Codasip Studio.

The Senior Hardware Engineer is responsible for the design and implementation of RISC-V processors, collaborating with teams on microarchitecture and verification, and ensuring design quality.