As a Hardware Verification Engineer at Codasip, you will verify RISC-V processors, create and maintain verification plans, automate tests, design solutions for process automation, and improve technologies through innovative ideas. Communication in English is essential due to the distributed nature of the team.

As an RTOS Engineer at Codasip, you will customize firmware, develop low-level software in C/C++, and enhance real-time operating systems for RISC-V CPU cores. You will support processor design teams, contribute to software innovation, and engage in both short and long-term projects. Strong embedded software development experience and a flexible approach are required.

As a CPU Design Engineer, you will design and develop next-generation CPU architectures, focusing on Out-of-Order cores and memory subsystems. Responsibilities include working on complex designs, collaborating with cross-functional teams, and utilizing proprietary tools like CodAL. You will also optimize modules for specific power, performance, and area (PPA) targets while applying your knowledge of hardware description languages and design synthesis flows.

As a Junior Hardware Verification Engineer at Codasip, you will ensure the quality and reliability of RISC-V processors by creating a robust verification environment, developing automated tests, and collaborating with design teams to meet functional requirements.

The Senior LLVM Compiler Engineer will customize and optimize LLVM compilers for embedded CPU cores, support software optimization, provide compiler expertise for microarchitectural design, and explore novel compiler technologies. The engineer will work on projects related to RISC-V technology and engage in both short-term and long-term strategic product development.

The Senior/Principal Verification Engineer will lead the verification team in developing strategies, architectures, and test plans for CPU microarchitecture. Responsibilities include creating test benches, driving bug analysis, and participating in design reviews, with a focus on RISC-V architecture.

The Hardware Design Engineer will define and implement microarchitectures for RISC-V processors, collaborate with teams on verification, optimize designs for performance, and utilize tools for synthesis and automation.

The Principal Verification Engineer will verify advanced RISC-V processors, develop verification solutions, collaborate with teams, define verification strategies, run simulations, and mentor junior engineers. Responsibilities include ownership of verification activities and crafting automated flows for debugging and root cause analysis.

The Formal Verification Engineer will be responsible for applying formal verification techniques to Codasip processors, reviewing FV test plans, developing tools, and ensuring the quality of RISC-V processor deliverables. Responsibilities include enabling formal verification users and contributing to innovative processor designs.

The CPU Design Engineer at Codasip will innovate and develop high-performance CPU cores based on RISC-V architecture using Codasip Studio and CodAL. Responsibilities include customizing IP cores, participating in design verification, and reporting results at international venues, requiring hands-on experience in processor development and background in digital design and embedded systems.

As a Digital HW Verification Engineer, you will verify digital IP blocks and validate the functionality of application-specific FPGA platforms. This involves testing the complete FPGA system before release and using skills in hardware verification and HDL languages like VHDL and Verilog, among others.

The Senior FPGA/Hardware Design Engineer will develop RISC-V-based FPGA platforms, integrating systems, prototyping, and collaborating with teams on technical challenges. This role involves both short-term customer projects and long-term strategic initiatives and requires strong problem-solving and FPGA development expertise.

The HPC System (SoC) Program Manager will lead a strategic semiconductor program aimed at designing a high-performance RISC-V CPU within a European consortium. Responsibilities include managing deliverables, coordinating with R&D project managers, developing program plans, and driving effective communication and reporting.

As a Hardware Verification Engineer at Codasip, you will verify modern RISC-V processors, create high-quality verification plans, develop pre-silicon verification environments, automate processes, and identify bugs. The role encourages innovation and allows you to contribute your ideas to improve technologies.

The Principal FPGA/Hardware Design Engineer will lead the development of RISC-V based FPGA platforms, set technical direction, mentor engineers, and collaborate on system integration and prototyping. Responsibilities include working with verification engineers, managing customer-driven projects, and performing RTL design and peripheral IP design.

The Hardware Design Engineer will develop RISC-V processors, focusing on microarchitecture definition, block specification, design synthesis, and performance optimization. The role involves collaboration with the verification team and using the proprietary CodAL language for processor development.

As a Senior Hardware Engineer at Codasip, you will be responsible for the microarchitecture definition and implementation of RISC-V processors, work on design synthesis, collaborate with verification teams, and produce technical documentation. This role involves leading complex design projects in a dynamic international environment.

As a CPU HW Engineer at Codasip, you will innovate and develop RISC-V based (micro-)architectural IP cores using Codal in Codasip Studio. Responsibilities include customising existing IP cores, contributing to design verification, and presenting technical results at international venues. Collaboration with academic and industry partners is essential, alongside hands-on experience in digital design and embedded systems.

As a Hardware Verification Engineer at Codasip, you will design and develop high-performance CPU cores using the RISC-V architecture. You will engage in hardware verification through simulation and formal tools, utilizing software skills in C++ or Python, and contribute to innovative processor optimization technology.

The C++ Developer will work on the CodAL team to develop a compiler for CodAL, maintain the language specification, ensure high code quality through unit testing, and optimize performance and code size. The role demands collaboration within a team and an agile mindset.