The RF System Engineer will manage RF systems from definition through integration, focusing on technical budgeting, simulations, noise and signal analysis. Key responsibilities also entail developing algorithms and specifications for radio frequency systems, as well as conducting hands-on lab work.

As an RTL Designer/Micro-architect, you will design innovative communication systems, tackle architectural challenges, and handle detailed implementation. You must leverage your strong Verilog/System-Verilog expertise and collaborate with a team to achieve project goals.

The Senior Verification Engineer will oversee the verification of high-speed communication digital design blocks, engage with design engineers to ensure specification compliance, and develop verification environments using SystemVerilog and UVM. Responsibilities include executing verification cycles, debugging functionalities, and ensuring full functional coverage through metric tracking.

The Mixed-Signal Verification Team Lead will manage a distributed team, collaborate with design teams to establish specifications, and drive the verification processes for mixed-signal designs. Responsibilities include overseeing the development of behavioral models, debugging verification issues, and mentoring team members while ensuring successful project deliveries.

As an Algorithm Engineer, you will develop and simulate DSP architectures and algorithms for coherent optical transceivers, interact with cross-functional teams, and ensure efficient implementation of circuit architecture.

As an Embedded SW Engineer, you will develop and maintain a Linux-based chip management application, implement test suites, optimize testing processes, and collaborate with international teams to ensure smooth integration and meet project deadlines.

The DFT Tech Lead will define, implement, and deploy advanced design-for-test methodologies for complex digital and mixed-signal chips, focusing on silicon test strategies and DFT architecture. Responsibilities include creating DFT specifications, debugging, and ensuring high test quality through design rule checks and logic insertion.

The Verification Team-Leader will lead and mentor a team of verification engineers, define verification strategies for complex digital blocks, develop robust verification environments, and collaborate with design engineers to resolve functionality issues. They will also report progress and risks to management while fostering a culture of technical excellence within the team.

The job involves developing high-end ADC and DAC in an advanced process for optical communication. You will work extensively with Cadence layout tools and TSMC FIN FET technology while collaborating with a team to ensure high-quality layouts meet specified high-speed and low-noise requirements, including tape-out procedures.

As a Layout Designer, you will focus on developing high-end ADC/DAC circuits using advanced processes for optical communication. The role requires strong expertise in layout tools, a solid understanding of TSMC technologies and tape-out procedures, and collaboration in a team environment.

The ASIC Back-End Engineer will be responsible for working on complex backend designs with a focus on low-power architecture, managing the full RTL2GDSII process, integrating IPs, and ensuring timely delivery while collaborating with external vendors.

The Senior Verification Engineer will lead the verification of digital design blocks, develop verification environments in SystemVerilog and UVM, and collaborate with design engineers on functionality and corner-case coverage.

As a DFT Engineer, you will be responsible for implementing advanced design-for-test methodologies on highly complex digital and mixed-signal chips, defining DFT strategies, and debugging silicon for ATE. You will collaborate with design teams to ensure test quality and document DFT processes.

Lead and manage a team of verification engineers, execute verification strategies, oversee the development of verification environments, and collaborate with design engineers to debug issues. Foster continuous learning within the team and report progress to senior management.

The Analog Designer will develop advanced analog mixed-signal circuits, including high-end ADC/DAC for optical communication. Responsibilities include design from concept through tape-out, focusing on performance aspects such as speed, power and noise, while collaborating with teams and external vendors.

As a Senior Back End Engineer at a well-funded startup, you will design and implement high-performance backend systems. Responsibilities include RTL2GDSII flow management, logic synthesis, timing analysis, and integration of complicated IPs, while ensuring low power consumption and working with external vendors.

The Mixed Signal Verification Engineer will focus on behavioral modeling of analog designs for digital verification and mixed signal dynamic verification. The role requires expertise in Verilog/SystemVerilog coding and experience with Virtuoso Schematics tools, ensuring effective verification of analog/mixed-signal designs in a collaborative environment.

The Mixed Signal Verification Engineer will engage in behavioral modeling of analog designs for digital verification, utilize chip digital design tools for mixed signal verification, and write Verilog/SystemVerilog code. They will also work with Virtuoso Schematics and employ verification methodologies to develop test cases in a collaborative team environment.