Description
For an exciting well-funded start-up, we are looking for layout engineers.
You will develop high end ADC/DAC in an advanced process for optical communication.
Requirements
Minimum Qualifications
Experience of 3+ years in sub micro process (3n up to 16n TSMC)
This experience must include:
- Expertise in Cadence Layout tools
- TSMC FIN FET technology design
- Good understanding of schematic flow
- Team work
- Strong understanding of high speed low noise layout requirements
- Experience in tape-out procedures
Preferred Qualifications
- Highly motivated
- Learning abilities
- Good communication
- Experience in both Mentor and Cadence tools is an advantage
What We Do
We are a semiconductor startup that has brought together a world-class team of ASIC designers, optical communications experts and seasoned investors that excel at creating disruptive technologies.
Together, we are building a novel semiconductor technology that will transform the datacenter and telecommunications industries.
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