SystemVerilog/UVM/ASIC Design Verification Engineer

Company Description

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Job Description

Role: Design Verification Engineer

Location: San Francisco, CA - Santa Clara, CA

Job Type: Contract

Interview: Phone/Video

Join our team to verify and validate cutting-edge SOC designs!

Key Responsibilities:

• Work on subsystems with multiple processors (ARM/RISC) and NOC

• Utilize UVM-based SoC verification and write basic tests in C

• Engage in design verification involving concurrency and memory access

• Define and implement SoC verification plans

• Develop functional tests and drive design verification to closure

• Debug and resolve functional failures in collaboration with the Design team

• Collaborate with cross-functional teams to ensure high design quality

• Drive continuous improvements in design verification

Experience & Skills:

• 8-10 years in SystemVerilog/UVM methodology/Assertions/functional coverage

• Proven track record of 'first-pass success' in ASIC development cycles

• Bachelor's degree in Computer Science, Computer Engineering, or related field

• Experience in ARM-based SoC verification

• Proficiency with EDA tools and scripting languages (Python, TCL, Perl, Shell)

• Knowledge of C or C++

Additional Information

All your information will be kept confidential according to EEO guidelines.