Fabric Cryptography

Principal CPU Digital Verification Engineer

Posted 13 Days Ago

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San Francisco, CA

Hybrid

Senior level

Hardware • Software

The Role

As a Principal CPU Digital Verification Engineer, you will contribute to the architecture and methodology of the verification environment, develop and execute verification plans, and work on the verification of processors and SoC designs. You will utilize formal and UVM verification methods while providing technical guidance to team members.

Summary Generated by Built In

Fabric believes hardware determines the boundaries of humanity's collective creativity and imagination. We are building hardware for the next generation of cryptography because we believe in creating a more trustworthy world with secure, private computation at its core. Just as encryption and decryption enabled the Internet as we know it, this new paradigm of cryptographic algorithms, such as zero knowledge proofs, have even broader potential to revolutionize how trust, privacy, and identity work in our society.

About the job

We are currently looking for CPU Digital Design Verification Engineers to join our team of brilliant, passionate people helping to create this breakthrough technology.

What you’ll be doing

Contribute to the architecture and methodology of our DV environment and team from scratch.
Develop and execute verification plans and test-benches to validate the functionality of our products.
Work on verification of processor architecture, PCIe/memory controllers, SoC, and Network on chip (NOC) structures
Write and maintain directed and constrained random tests to ensure that the verification environment is up-to-date and effective.
Work cross functionally to integrate the verification environment into the overall design flow.
Own and develop formal and UVM verification methods to ensure the completeness and consistency of the design.
Provide technical guidance to other team members with the latest verification best practices and techniques.

Qualifications and experience requirements

BS, MS, PhD in Electrical Engineering, Computer Science, or a related field.
10+ years of strong experience with design verification, including simulation and formal verification.
Core CPU pipeline Design Verification experience, VLIW knowledge a plusCreating and using ISA random test generators
Using DPI to integrate golden reference models
UVM testbench development from scratch, SystemC/C++ experience a plus
Python knowledge and scripting/automating DV flows
Good understanding of digital design, including RTL design, UVM, System Verilog and synthesis.
Knowledge of cryptography and data protection is a plus.
Excellent written and verbal communication skills, and the ability to work effectively in a team environment.
Ability to work independently, under pressure and in a startup setting.