Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
Job Description
We are looking for a Digital Design Manager with experience developing microarchitecture and implementing front-end circuit design, including RTL, synthesis, IP integration, and block-level verification, for high-performance network controllers' connectivity solutions. The candidate must have a good knowledge of communication and interface standards and base protocols such as PCI-Express (Gen-3 and above), Ethernet, NVMe, DDR, etc.
Basic Qualifications:
- Strong academic and technical background in Electrical or Computer Engineering. A bachelor's EE is required, and a Master's degree is preferred.
- 12+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- 3+ years’ experience in technical leadership or management experience.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare in advance for customer meetings, and work mostly independently with minimal guidance and supervision.
- Entrepreneurial, open-minded, and with a can-do attitude. Think and act fast, always keeping the customer in mind!
- Authorized to work in the US and start immediately.
Required experience:
- Hands-on, thorough knowledge of at least one high-speed protocol such as PCIe, CXL, Ethernet, NVMe, DDR etc.
- Proven front-end design expertise in architecture, RTL, simulations, synthesis, timing closure, GLS, DFT, etc.
- Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production. Extensive collaboration with software development teams is needed.
- Experience using Cadence and/or Synopsys digital design tools/flows.
- Knowledge in design for test (DFT), stuck at, and transition scan test insertion.
- Familiarity with UVM-based design verification
- Silicon bring-up and debug expertise
- Small-geometry CMOS (≤ 28nm, 16nm) design
Preferred experience:
- Scripting with Python or other equivalent programming languages.
- Development/support for PCIe and DDR-based products. PCIe or Ethernet Switch products. Familiarity with security standards
- Strong methodology mindset with a track record of developing ASIC development methodologies.
The base salary range is $184,000 USD – $260,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Top Skills
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center.
Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning.
The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
