Principal Application Engineer

Posted One Month Ago
Be an Early Applicant
2 Locations
Remote
175K-195K Annually
Expert/Leader
Semiconductor
The Role
Lead technical efforts on high-speed chiplet and interconnect technologies, providing customer engagement and engineering support while ensuring compliance with industry standards.
Summary Generated by Built In

The Opportunity

We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Why Join Us?

  • Work on cutting-edge chiplet and high-speed interconnect technologies that define the future of semiconductor innovation.
  • Collaborate with leading semiconductor companies, foundries, and IP vendors in the growing Die-to-Die interconnect ecosystem.
  • Be a part of a high-impact team driving next-generation computing architectures.

1. Technical Leadership & Customer Engagement

  • Serve as the primary technical expert for UCIe, SerDes, and other D2D interfaces, working closely with customers, SoC architects, and design teams.
  • Provide pre-sales and post-sales technical support, helping customers with architecture selection, integration challenges, signal integrity (SI), and power integrity (PI) considerations.
  • Work closely with foundries, IP vendors, and ecosystem partners to enable seamless chiplet-based integration.
  • Conduct customer training, workshops, and documentation for UCIe and SerDes-based solutions.

2. Applications Engineering & Product Development

  • Drive application engineering efforts for Die-to-Die interconnect solutions, ensuring performance, compliance, and robustness across various process nodes.
  • Optimize PHY, link-layer, and protocol-layer implementations for high-speed SerDes and UCIe-based interconnects.
  • Collaborate with design, verification, validation, and software teams to support silicon bring-up and debugging.
  • Analyze and optimize latency, bandwidth, and power efficiency of UCIe and SerDes interfaces.

3. System-Level Debugging & Validation

  • Assist in post-silicon validation, testing, and debug of high-speed D2D interconnects.
  • Work with test and characterization teams to analyze real-world performance and optimize system-level performance metrics.
  • Provide technical feedback to design teams for future IP enhancements and roadmap alignment.

4. Standards Compliance & Ecosystem Contributions

  • Stay up to date with UCIe, SerDes, and related industry standards to ensure compliance and interoperability.
  • Contribute to industry forums, standardization committees, and working groups for Die-to-Die interconnect technologies.
  • Drive internal discussions on next-generation chiplet interconnect technologies and contribute to IP roadmaps.

What you'll do:

  • Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related field with 10+ years of experience in high-speed interface design, applications engineering, or silicon bring-up.
  • Strong expertise in Die-to-Die interconnect technologies, including UCIe, SerDes, HBM, and other chiplet-based interconnects.
  • Hands-on experience with signal integrity (SI), power integrity (PI), and high-speed serial interfaces.
  • Strong knowledge of SoC architecture, PHY design, package integration, and advanced process nodes (e.g., 5nm, 3nm, etc.).
  • Experience with simulation tools (HFSS, Ansys, ADS), lab equipment (Oscilloscopes, BERT, VNA, etc.), and debugging methodologies.
  • Familiarity with protocols such as PCIe, CXL, Ethernet, and memory interfaces is a plus.
  • Proven ability to engage with customers, provide technical support, and drive adoption of new technologies.

Nice to Have:

  • Experience in chiplet-based system design and heterogeneous integration.
  • Contributions to UCIe Consortium, SerDes standardization efforts, or IEEE working groups.
  • Hands-on experience with silicon bring-up, post-silicon debug, and validation methodologies.

We have a flexible work environment to support and help employees thrive in personal and professional capacities.

Salary and Benefits

Your contribution will be recognized with a base salary within the range of $175,000 to $195,000 annually as It is influenced by your qualifications, experience, location, and the internal equity of our team to ensure fairness and consistency across roles. In addition to our comprehensive benefits package, employees are also eligible for additional compensation opportunities, including a short-term incentive program, Retirement & Saving Programs and participation in the Employee Stock Purchase Plan (ESPP)

You'll also be eligible for competitive benefits described as per below:

Health & Wellness

Our programs emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage.

  • Comprehensive health plans
  • Wellness Spending Account (WSA)
  • Employee Assistance Program (EAP)

Time Off

We value the importance of rest and recharge, which is why we offer flexible time off options to support your well-being.

  • Paid Vacation
  • Paid Holidays
  • Parental Leave

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Top Skills

Ads
Ansys
Cxl
Ethernet
Hbm
Hfss
Pcie
Serdes
Ucie
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The Company
HQ: Toronto, Ontario
636 Employees
On-site Workplace
Year Founded: 2017

What We Do

We work to create silicon that enables the highest performing, most reliability and lowest power digital communication networks.

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