The role involves designing and optimizing embedded firmware for high-speed SerDes PHYs, collaborating with multiple teams, debugging, and developing automation for testing.

Develop and test verification environments for high-speed products, collaborating with Design and Algorithm teams, and utilizing SystemVerilog UVM.

Oversee technical accounting operations, ensure financial reporting compliance with standards, guide complex accounting issues, and support business financial processes.

The role involves owning and executing physical verification flows and reviewing project finishing activities. Responsibilities include analyzing and debugging various physical checks using Calibre and ICV, addressing PV issues in collaboration with the PD team, and contributing to SoC-level PV sign-off checks.

As an RTL Design Engineer, you will microarchitect and design SoC subsystems, develop documentation, ensure design quality, and collaborate with verification and physical teams for successful SoC performance.

The Sr Director of Internal Audit will develop audit strategies, oversee compliance and risk management initiatives, manage a team of auditors, and partner with leadership to enhance governance and controls.

Lead verification for UCIe, PCIe, and MMU subsystems in ARM-based SoCs, collaborate with teams, and develop scalable testbench components.

Oversee HR operations, ensure compliance, manage the HR team, enhance employee experience and engage in process improvement and data analysis.

As a Product Engineer, you will validate and characterize ultra-high-speed interfaces in semiconductor designs, focusing on data analysis and reporting.

The Senior HR Business Partner aligns HR initiatives with business objectives, driving talent management, employee engagement, and organizational development while advising senior leadership.

Responsible for end-to-end verification of features in ASIC design, analyzing test failures, and collaborating with cross-functional teams to improve verification processes.

You will architect and develop IP blocks for CXL/PCIE ASICs/FPGA, lead projects, streamline processes, and manage team development.

Lead global tax strategy, compliance, and reporting. Manage tax audits, optimize tax positions, and improve processes while overseeing international tax regulations.

The Staff Engineer will design and develop microarchitecture and RTL for SoC subsystems, collaborate across teams, and ensure design quality and successful tapeout.

The Principal Engineer will oversee chiplet architecture and design, focusing on RTL design, microarchitecture documentation, and hardware quality checks throughout the ASIC development cycle.

The role involves microarchitecting, RTL design of SoC subsystems/IP blocks, collaborating with various teams for successful ASIC development and tapeout.

Manage the design team for SoC development, providing technical support and ensuring project goals are met through collaboration with cross-functional teams.

As an RTL Design Engineer at Alphawave Semi, you'll engage in the complete ASIC development cycle, responsible for microarchitecture coding, documentation, and collaborating with verification and physical design teams to ensure quality SoC designs.

The Senior HR Business Partner will partner with leadership to implement HR strategies, enhance employee engagement, manage organizational change, and ensure compliance with policies.

The Senior Product Line Manager will drive product strategy and development for high-speed semiconductor products, ensuring alignment with customer needs and market trends.