Search the 63 jobs at Alphawave IP, Inc.

You will manage the design and RTL team, propose architecture solutions to customers, oversee project goals, and improve flow and methodology in ASIC design. The role requires interaction with clients for technical support and collaboration with team members and IP vendors to ensure project delivery.

The Senior Engineer in Physical Design at Alphawave Semi will handle hands-on physical design and verification tasks, manage ASIC development flows, and mentor junior team members. Responsibilities include floor-planning, place and route, timing closure, and physical verification tasks like DRC and LVS checks.

The Staff Engineer will handle physical design and verification tasks in advanced ASIC projects, manage development flows, and mentor junior team members. Responsibilities include floor-planning, place and route, timing closure, and addressing verification issues. The role emphasizes quality control in design databases and IP integration.

The Senior DFT Engineer will design and implement DFT architecture for HSIO IP and SoC designs, generate and insert DFT structures, produce ATPG patterns, run timing analysis, and mentor junior engineers. They will engage in diagnostics and failure analysis for customer returns.

As a Staff DFT Engineer, you will lead the development of methodologies and flows for integrated RTL-centric DFT environments, manage teams, create automated verification test benches, and ensure the quality of design implementation through various DFT standards. This role requires collaboration and mentorship throughout the project lifecycle.

As an Engineer II - VLSI, you will be responsible for the verification of IP, Block, or Subsystem at SoC Level. Your role involves generating verification documentation, analyzing and debugging verification tasks, and developing your own verification environments and components. You will collaborate with the Lead Engineer.

As a Logistics Specialist, you will manage and coordinate import and export shipments, ensuring compliance with international regulations, preparing shipping documents, liaising with customs and logistics partners, and maintaining accurate transaction records to optimize shipping efficiency.

The Senior Engineer I - ASIC Design at Alphawave Semi will handle physical design and verification tasks for ASIC projects, managing development flows, and conducting various checks and analyses to ensure effective design within advanced process nodes. A strong background in high-speed designs and experience with specific tools is required.

The position involves designing and verifying VLSI chips, including tasks like RTL design, creating test environments, and setting up physical design flows. Candidates will work on cutting-edge technology nodes while ensuring compliance with design rules and performance metrics.

As a Test Engineer Manager, you will manage a team of test engineers, oversee ATE test module development, collaborate across various teams for product launch, and ensure high-quality testing standards. Responsibilities include mentoring team members, leading design and implementation of testing processes, and traveling to vendor sites as needed.

As a SoC/System Architect, you will drive the architecture of ARM Neoverse-based chiplets, define system-level use cases, document performance metrics, and collaborate with design teams while engaging with customers for pre-sales activities. You will specify IP and document architecture and integration.

The Principal Digital Verification / Lead Engineer will lead the verification team, overseeing the verification process for ARM Neoverse-based Multi-CPU SoCs. Responsibilities include developing verification plans, creating reusable testbenches, mentoring junior members, and collaborating with design teams to ensure accurate verification of subsystems and architectures.

In this role, you will manage all aspects of the US immigration process, including client communication, document gathering, and application submission for various visa types. The position involves preparing petitions, providing consular support, and improving processes while meeting client deadlines.

The Staff Engineer I for STA and Synthesis will lead static timing analysis and synthesis for complex ASIC designs, collaborate with various teams on timing optimization, and develop timing constraints using scripting languages. The role emphasizes leadership and communication skills to drive design closure and efficiency, while staying updated with emerging technologies in ASIC design.

As a Senior Staff Engineer I - RTL Design, you will lead the design and architecture of SoCs and micro-architecture, manage a design team, engage in pre-sales support, and ensure timely project delivery. Your expertise will support customers in implementing data communication solutions across various applications while fostering improvements in design methodologies.

As a Senior Engineer in Physical Design, you will drive the backend processes of IC design, focusing on floor-planning, power planning, low-power design, place & route, and static timing verification. You'll perform physical verification and EM/IR signoff to optimize power integrity and timing closure. The role requires collaboration, analytical skills, and a commitment to high-quality results.

The Design Verification Engineer will lead the verification of new customer features, review design specifications, build testbenches, and analyze test failures. The role involves collaborating with multiple teams, integrating third-party VIPs for compliance testing, and contributing to the improvement of verification methodologies.

Responsible for verification of IP, Block, or Subsystem at SoC Level, generating documentation, debugging verification tasks, and developing the verification environment and components. Requires a strong understanding of functional verification and experience with various interfaces and methodologies.

The Senior Engineer II - ASIC Design will focus on accelerating critical data communication technologies for sectors such as AI, 5G, and autonomous vehicles, contributing to innovative solutions in a diverse workplace.

In this role, you will lead the verification of IP and sub-systems, develop scoreboard mechanisms and monitoring for issue detection, create verification environment components, code tests and assertions, and ensure functional coverage while debugging failures and managing regression testing.