You will architect and develop IP blocks for CXL/PCIE ASICs/FPGA, lead projects, streamline processes, and manage team development.

Lead global tax strategy, compliance, and reporting. Manage tax audits, optimize tax positions, and improve processes while overseeing international tax regulations.

The Staff Engineer will design and develop microarchitecture and RTL for SoC subsystems, collaborate across teams, and ensure design quality and successful tapeout.

The Principal Engineer will oversee chiplet architecture and design, focusing on RTL design, microarchitecture documentation, and hardware quality checks throughout the ASIC development cycle.

The role involves microarchitecting, RTL design of SoC subsystems/IP blocks, collaborating with various teams for successful ASIC development and tapeout.

Manage the design team for SoC development, providing technical support and ensuring project goals are met through collaboration with cross-functional teams.

As an RTL Design Engineer at Alphawave Semi, you'll engage in the complete ASIC development cycle, responsible for microarchitecture coding, documentation, and collaborating with verification and physical design teams to ensure quality SoC designs.

The Senior HR Business Partner will partner with leadership to implement HR strategies, enhance employee engagement, manage organizational change, and ensure compliance with policies.

The Senior Product Line Manager will drive product strategy and development for high-speed semiconductor products, ensuring alignment with customer needs and market trends.

The Staff Engineer will lead SOC EMIR analysis, collaborate with teams for design changes, mentor juniors, and influence analysis workflows.

Lead the verification for SoC System Manager, oversee verification activities, collaborate with design teams, and develop scalable testbench components.

Design Engineer will manage the IO Memory Management Unit components for a multi-core Arm CPU based SOC, focusing on architecture, design, and STC integration while collaborating with teams on verification and debugging.

The Design Engineer will lead the Interrupt Subsystem components for multi-core ARM-based SoCs, conduct RTL coding and integration, and support design and validation activities within a collaborative engineering environment.

Define debug strategies for multi-core ARM SoC designs, create architecture documentation, integrate RTL, perform synthesis, and collaborate on debug processes.

The role involves hands-on ASIC physical design and verification, managing development flows, mentoring, and ensuring integration of designs.

The Senior Engineer I - DFT will lead DFT strategy, develop verification methodologies, automate test bench creation, and ensure timing checks for SoCs.

As a Principal Engineer in DFT, you will develop methodologies, manage teams, architect flows, and enhance automated verification for integrated circuits.

As a Staff Engineer I in DFT, you will develop methodologies, automate verification processes, mentor engineers, and manage DFT flows for complex designs across the company.

Lead development of DFT methodologies and flows, manage and mentor engineers, and ensure quality control in design verification across projects.

The Staff DFT Engineer will develop and manage DFT methodologies, automate verification processes, oversee team tasks, and mentor engineers for complex SoC designs.