Lead global tax strategy, compliance, and reporting. Manage tax audits, optimize tax positions, and improve processes while overseeing international tax regulations.

Looking for a Senior Engineer to innovate in ASIC design focused on enhancing data communication across various digital technologies including AI and 5G.

The role involves microarchitecting, RTL design of SoC subsystems/IP blocks, collaborating with various teams for successful ASIC development and tapeout.

As an RTL Design Engineer at Alphawave Semi, you'll engage in the complete ASIC development cycle, responsible for microarchitecture coding, documentation, and collaborating with verification and physical design teams to ensure quality SoC designs.

Contribute to the ASIC development cycle, focusing on microarchitecture and RTL design for SoC subsystems, ensuring successful integration and verification with various teams.

The Senior HR Business Partner will partner with leadership to implement HR strategies, enhance employee engagement, manage organizational change, and ensure compliance with policies.

The role involves hands-on physical design and verification of ASIC projects, managing ASIC development flow, mentoring junior team members, and ensuring integration of IP and pad-rings in designs. Key tasks include floor-planning, place and route, timing closure, and debugging.

The Senior Product Line Manager will drive product strategy and development for high-speed semiconductor products, ensuring alignment with customer needs and market trends.

The Staff Engineer will lead SOC EMIR analysis, collaborate with teams for design changes, mentor juniors, and influence analysis workflows.

The Design Engineer will lead the Interrupt Subsystem components for multi-core ARM-based SoCs, conduct RTL coding and integration, and support design and validation activities within a collaborative engineering environment.

Lead the verification for SoC System Manager, oversee verification activities, collaborate with design teams, and develop scalable testbench components.

Design Engineer will manage the IO Memory Management Unit components for a multi-core Arm CPU based SOC, focusing on architecture, design, and STC integration while collaborating with teams on verification and debugging.

Define debug strategies for multi-core ARM SoC designs, create architecture documentation, integrate RTL, perform synthesis, and collaborate on debug processes.

The Senior Engineer - STA will lead the timing convergence for SoCs, manage timing constraints, and oversee timing analysis and closure efforts.

Lead the timing convergence of SoCs, manage STA setup and full chip timing analysis, develop automation scripts, and collaborate with various teams for design and verification.

The role involves hands-on ASIC physical design and verification, managing development flows, mentoring, and ensuring integration of designs.

The Senior Engineer I - DFT will lead DFT strategy, develop verification methodologies, automate test bench creation, and ensure timing checks for SoCs.

As a Principal Engineer in DFT, you will develop methodologies, manage teams, architect flows, and enhance automated verification for integrated circuits.

Lead development of DFT methodologies and flows, manage and mentor engineers, and ensure quality control in design verification across projects.

The Staff DFT Engineer will develop and manage DFT methodologies, automate verification processes, oversee team tasks, and mentor engineers for complex SoC designs.