Logic Design Verification Engineer

Job Details:

Job Description: 

Seize the opportunity to work with the team responsible for RTL logic design and development of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for ISCP client projects. This job requisition is to seek an experienced, disciplined and collaborative design verification engineer in Malaysia.

• As a member of the Chipsets Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification.
• You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools.
• You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing.
• Your influence will cross organizational boundaries with our manufacturing and validation partners.
• Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools.

Qualifications:

• The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent.
• The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills.
• The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills.
• The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment.

Other technical requirements:

• 7+ years of relevant pre-silicon verification/logic design experience.

Experienced with various tools and methodologies including but not limited to:

• System Verilog, Python/Perl/Shell scripting, power-aware simulation with VCS/Synopsys tools, RTL model build, design-for-test, design-for-verification.
• Experienced in developing test plan and contents and coverage points for validation purpose based on High Level Architecture specifications.
• Experienced in VLSI or Structural and Physical design flow and methodology, SIP and HIP interoperability validation.
• Experienced in Power-aware design and validation flows.
• Experienced in AMBA, UFS, SPI, USB, PCI express or any industry standard BUS protocol.
• Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

Job Type:Experienced Hire

Shift:Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Additional Locations:Malaysia, Kulim

Business group:In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.