The Platform Hardware Architect leads the development of mobile platform hardware requirements, drives project milestones, manages integration, and collaborates with OEM architects on product development.

The EDA Tools Hardware Engineer will design, implement, and support hardware sign-off tools and methodologies, collaborating with vendors and design teams to enhance tool quality and efficiency.

The Physical Design Engineer will implement custom IP and SoC designs from RTL to GDS, ensuring design integrity and optimized performance through verification and analysis.

The CPLG Financial Analyst provides financial support to Corporate Planning and Logistics, including analysis, budget preparation, and variance explanations. They engage in cost reduction initiatives and ensure compliance with accounting standards.

Lead the Timing methodology and closure for custom SOC designs, focusing on enhancing product performance and power using industry standard tools.

Responsible for developing power integrity solutions for Intel client products, including package design and validation while using electrical simulation tools.

The Research Scientist Intern will focus on developing innovative graphics techniques using ML, collaborating on research, analyzing data, and contributing to Intel's graphics technology.

The role involves conducting power and performance validation for Intel CPU products through lab work, system calibration, and coordination with teams.

The intern will support PDK development for advanced process technologies, collaborating with experts and improving EDA tool usability.

This internship in the Design Technology Platform involves developing PDKs for Intel's advanced technologies while collaborating with various teams and experts.

The intern will support analytics and reporting solutions in Finance, focusing on data analysis, validation, and cloud-based data tools.

Assist in debugging, contribute to solution development, responsible for testing and validation, and create user documentation.

Lead verification for SOC designs, develop test plans, debug simulations, innovate methodologies, and mentor the team to enhance verification efficiency.

The Physical Design Engineer will create and optimize chip design elements, handle layouts, and verify complex chip developments while troubleshooting design issues.

Conduct verification of IP and/or SoC microarchitecture using formal verification methodologies, create test and coverage plans, and collaborate with design teams. Develop and review formal proofs while maintaining verification infrastructure and improving methodologies.

The Business Operations Manager will oversee go-to-market strategies, set KPIs, manage P&L operations, and collaborate across teams to optimize silicon foundry functions.

LTD Device Engineering Managers lead scientific research device groups, manage core process development on silicon technology, and ensure high-quality product performance through collaboration and extensive analysis.

The Business Development Manager influences strategic programs, develops government contracts, and collaborates with teams to secure new business opportunities in Japan.

Manage government contracts and programs, collaborate with internal and external partners, oversee budgeting, and ensure compliance with legal and procedural requirements.

Design, execute, and analyze experiments in semiconductor device development. Develop algorithms, conduct data analysis, and create applications to solve technical problems.