Search the 50 jobs at SiFive Inc

The Sr. Account Executive - Embedded Sales is responsible for driving sales of CPU IP into embedded segments, developing sales strategies, managing client relationships, achieving sales targets, conducting market research, preparing proposals, and collaborating with internal teams to meet customer needs.

The AI/ML Software Engineer will optimize and deploy AI/ML models on RISC-V architectures, develop performance algorithms, and collaborate with hardware engineers. Responsibilities include model profiling, algorithm development, and contributing to open-source projects. Candidates should possess strong programming skills in C/C++ and Python, along with experience in AI/ML development.

The Principal Verification Engineer at SiFive will oversee the verification of RISC-V based CPU IPs, ensuring their functionality and performance. Responsibilities include creating verification strategies, collaborating on microarchitecture design, and resolving verification challenges related to memory subsystems and caches.

The Principal Architect will develop scalable SoC architectures for custom chips, integrating various SoC IP components. The role focuses on creating multicore platforms for high bandwidth and innovative applications, utilizing modern EDA tools and RISC-V technology to expedite chip design and verification.

The Staff Engineer DV will architect test methodologies for CPU designs, develop effective verification strategies, create test plans, and build tools and test suites. This role involves collaborating closely with design teams and leading verification efforts to ensure program goals are met.

The Senior Engineer in Design Verification at SiFive will work on low power management and core microarchitecture, lead multiple projects, perform power simulation, and write scripts to assess power impact at various circuit levels. Candidates should possess strong problem-solving skills and adapt well in diverse environments.

Responsible for hands-on CPU verification using SV, UVM, and test generators. Requires 5-10 years of experience in CPU-based verification, proficiency in C and scripting with PYTHON, and knowledge of bus interface protocols.

As a Physical Flow Software Engineer, you will develop automated flows for SiFive's RISC-V Core IP, collaborating with cross-functional teams to define and implement features. This role focuses on building scalable and reusable tools that interface with physical design tools, ensuring the effective validation of RTL outputs.

The role involves leading a team in power convergence and modeling projects, emphasizing experience in AI/ML accelerators or GPUs. The candidate will conduct power simulation, ASIC power analysis, and optimization while scripting in Python, Perl, or Tcl. Strong communication skills are essential for presenting power status to management and product teams.

The Staff Engineer will focus on hands-on System Verilog and UVM development for high-performance CPU verification, including writing test cases, generating targeted tests for RISC-V CPU verification, and working with internal test generators to achieve coverage and test-plan goals.

The Staff Formal Verification Engineer will implement and maintain formal verification environments, create formal test-plans, and lead the application of various formal verification techniques. Responsibilities include debugging RTL, developing automation scripts, guiding team members, and reviewing proofs with design teams.

The Functional Safety Architect will contribute to SiFive's FuSa/RAS solution portfolio, ensuring seamless integration across IPs and collaborating with engineering and product teams to derive requirements for failure detection and response solutions.

The principal physical design lead is responsible for leading the implementation and optimization of high-performance Out of Order RISC-V CPUs from RTL to GDSII, focusing on performance, power, and area goals, collaborating with teams to drive PPA trade-offs, and contributing to physical implementation flow development.

The Verification Engineer at SiFive will ensure the fidelity of new RISC-V based CPU IPs by adopting advanced verification methodologies. Responsibilities include creating test plans, executing tests, and ensuring design quality through coverage metrics, while working alongside a high-performance CPU team on components such as Frontend and Execution Units.

The role involves leading a team focused on power convergence, reduction, and modeling for high-performance cores. Responsibilities include managing power simulations, ASIC power analysis, and presenting power status to various teams. The candidate should have extensive experience in out of order core microarchitecture and strong scripting skills in Python, Perl, or Tcl.

The Principal System and Software Architect will design and implement RISC-V computing platforms while collaborating cross-functionally to deliver advanced CPU cores and systems. Responsibilities include developing software for SiFive hardware features, creating architectural specifications, and planning complex projects within a cross-functional engineering team.

The Software Engineer will develop and maintain software applications using Java and Python, enhance data flow scripts, and manage both production and non-production environments. The role includes collaboration with software engineers and business stakeholders in a scrum-based CI/CD environment, focusing on building scalable and resilient applications, as well as dashboard design.

As a FuSa/RAS design engineer, you will architect and implement new features for RISC-V CPU cores, support safety analysis, perform verification, and collaborate with physical design teams while creating high-quality documentation.

The Senior Software Engineer will implement key business logic and data movement in product design workflows, write automation for development tools, maintain the codebase, and enhance architecture and code quality while interfacing with other teams.

The Fusa/RAS Architect will contribute to creating a robust FuSa/RAS solution portfolio, collaborate with engineering teams for optimal implementation, analyze requirements to detect failures, and support product teams to identify customer needs in functional safety and RAS.