Search the 56 jobs at SiFive Inc

The Senior CPU Design Verification Engineer will collaborate with multiple teams to generate, triage, and debug test cases for CPU design. Responsibilities include analyzing random test cases to improve verification coverage and supporting the execution of generators in the RTL design process.

This role involves architecting test methodologies for CPU memory subsystems, developing verification strategies, creating test plans, building test benches, and providing technical leadership for verification engineers. Collaboration with design teams on specifications and failure analysis is key.

The Principal Verification Engineer will oversee the verification of highly configurable RISC-V based CPU cores, ensuring they function correctly in various applications like autonomous driving and IoT. Responsibilities include developing verification strategies, collaborating with design teams, and enhancing verification quality through innovative techniques and metrics.

As a Staff Design Verification Engineer, you'll collaborate with various teams to generate automated test cases, develop verification tools and test benches, and ensure coverage-driven testing for memory subsystems.

The Principal Performance Tools Engineer at SiFive leads the development of performance simulation tool suites for next-generation processors. Responsibilities include collaborating with partners, defining tool requirements, and guiding a team in executing the vision for these tools.

The Principal Performance Pathfinding Engineer will lead a team to research and develop high-performance processor architectures and micro-architectures. This includes defining performance targets, conducting experiments, and collaborating with design teams to meet delivery goals.

The role involves supporting customers in evaluating SiFive products, optimizing performance, and developing customized solutions. It combines workload characterization, hardware and software development practices to enhance CPU designs while collaborating with internal and external teams for effective customer engagement.

The Staff Hardware Application Engineer will support customers using SiFive IPs, resolve integration issues, collaborate with engineering and sales teams, deliver training, and improve documentation. The role requires strong communication skills and expertise in CPU and bus architectures.

The Sr. Staff Field Applications Engineer will drive pre-sales technical engagement with customers regarding CPU and SoC architecture. Responsibilities include managing customer evaluations, demos, and benchmarks, collaborating with sales to meet targets, and articulating technical requirements to internal stakeholders.

The Staff Engineer at SiFive will be responsible for hands-on system Verilog/UVM development and modern high-performance CPU verification, including writing test cases and using test generators for RISC-V CPU verification. The role also involves working with internal tools to target specific coverage and test-plan scenarios.

The Senior Staff Engineer will develop and manage the software roadmap for SiFive development boards, support Linux distributions, collaborate with internal and external teams, and ensure best practices in open source software are followed. This role requires hands-on expertise in system software development.

The role involves leading a team in power convergence and modeling, focusing on power simulation and ASIC power analysis. The candidate will drive projects, utilize scripting skills in Python, Perl, or Tcl, and communicate power status across teams.

Lead the implementation and optimization of SiFive's high-performance Out of Order RISC-V CPUs, collaborating with RTL teams to achieve performance, power, and area goals. Contribute to physical implementation flow and Foundation IP improvements, fostering teamwork and high-quality design in the process.

The Sr. Staff System and Software Architect will design and implement advanced RISC-V computing systems, focusing on both software and hardware architecture. Responsibilities include collaborating with global teams, developing low-level code for operating systems, and writing specifications for new features. This role emphasizes scalability, performance, and cross-functional collaboration in creating innovative computing solutions.

As a Staff Software Engineer, you will architect and implement features and internals for a compiler related to RISC-V, develop tools for the language ecosystem, and design quality code to meet expanding business requirements while interfacing with various teams in SiFive.

The AI/ML Software Engineer will optimize and deploy AI/ML models on RISC-V architectures, develop performance algorithms, and collaborate with hardware engineers. Responsibilities include model profiling, algorithm development, and contributing to open-source projects. Candidates should possess strong programming skills in C/C++ and Python, along with experience in AI/ML development.

The Debug, Trace and Profiling Architect at SiFive will define platform requirements and architectural features for debug, trace, and profiling solutions. They will engage with customers to understand needs, interact with various architectural teams, and develop microarchitecture specifications in a collaborative environment.

The Principal Architect will design scalable SoC architectures, customize chips for various use cases, research emerging needs, and interface with clients to tailor SoCs. Responsibilities include developing multicore platforms and collaborating with Fortune 500 companies on advanced chip designs.

The Senior Engineer in Design Verification at SiFive will work on low power management and core microarchitecture, lead multiple projects, perform power simulation, and write scripts to assess power impact at various circuit levels. Candidates should possess strong problem-solving skills and adapt well in diverse environments.

Responsible for hands-on CPU verification using SV, UVM, and test generators. Requires 5-10 years of experience in CPU-based verification, proficiency in C and scripting with PYTHON, and knowledge of bus interface protocols.