The Director of Physical Design will lead the implementation of RISC-V IPs, optimize performance, power, and area, and improve customer experiences in physical design processes.

The role involves optimizing RISC-V CPU implementations from RTL to GDSII, focusing on achieving performance, power, and area goals while collaborating with design teams.

As a Physical Design Engineer, you will optimize RISC-V CPUs from RTL to GDSII, achieve performance goals, and collaborate on physical implementation flows.

The DFT Design Engineer will implement and validate MBIST, Scan, and LBIST across various Processor Core IP Subsystems, collaborating with RTL designers and ensuring design quality.

Lead power convergence and modeling projects, manage teams, and focus on AI/ML accelerators or GPUs while optimizing ASIC power.

Lead the implementation of AI/ML accelerator IP from RTL to GDS, focusing on optimizing power, performance, and area (PPA) in collaboration with design teams.

Drive timing convergence of high-performance designs, develop timing analysis infrastructure, and improve productivity of physical design team.

The Power UPF Methodology Engineer will drive UPF methodology implementation, work on low power design, and manage power intent verification at chip level while collaborating with various teams.

The Sales Director will drive customer base growth for SiFive IP products in North America, manage key relationships, define technical needs, and develop strategic sales plans.

This role involves leading power convergence and modeling efforts, managing engineering teams, and optimizing power analysis for high-performance cores.

The role involves leading design verification for power management and simulation, focusing on architectural impacts and requiring strong problem-solving skills.

Develop and optimize high-performance machine learning algorithms and software libraries for RISC-V hardware, collaborating with architects and engineers on product development.

The Staff Hardware Application Engineer will support customers with SiFive IP, resolve technical issues, deliver training, and collaborate internally.

The Staff Engineer will focus on CPU verification through hands-on experience in writing test cases, creating test plans, and debugging, with proficiency in multiple programming languages and verification methodologies.

The software engineer will collaborate on system infrastructure for SiFive’s products, focusing on modular software flows, APIs, and validation with design engineers.

Architect and implement features and compiler internals for a functional programming language, enabling development and delivery of SiFive’s RISC-V core IP product.

Develop debugging and profiling tools for RISC-V processors, improve existing tools, engage with other engineering teams, and provide customer support.

As a Senior Staff System and Software Architect, design and implement RISC-V platforms, focusing on software and hardware architecture. Collaborate with global teams and create architectural specifications for advanced CPU cores and subsystems.

Responsible for hands-on System Verilog/UVM development for CPU verification, creating test cases, and using generators for targeted tests.

Lead the physical design implementation of RISC-V IPs, ensure performance goals, automate design flows, and enhance customer experience.