MatX

HQ
Mountain View, California, USA
19 Total Employees

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Jobs at MatX

Search the 6 jobs at MatX

Recently posted jobs

10 Hours Ago
Mountain View, CA, USA
Artificial Intelligence • Hardware • Software
The Software Engineer will develop and maintain functional and performance models of hardware, create tools for testing and debugging, collaborate across teams, contribute to architectural reviews, and implement performance optimizations.
10 Hours Ago
Mountain View, CA, USA
Artificial Intelligence • Hardware • Software
The DevOps/IT Specialist will optimize and secure the IT infrastructure at MatX, develop scalable cloud architectures, manage cloud resources, ensure security compliance, automate operations using IaC, troubleshoot IT issues, and collaborate with engineering teams on cloud service integrations.
10 Hours Ago
Mountain View, CA, USA
Artificial Intelligence • Hardware • Software
The Software Engineer will design and implement compilers tailored for proprietary hardware, offering insights on hardware architecture. Responsibilities include focusing on mid-end and backend development, with a strong emphasis on efficiency and performance in compiler algorithms.
10 Hours Ago
Mountain View, CA, USA
Artificial Intelligence • Hardware • Software
As an ML Performance Engineer, you will build performance models and tooling for ML models, write libraries for efficient distributed training, and collaborate with hardware and software teams.
10 Hours Ago
Mountain View, CA, USA
Artificial Intelligence • Hardware • Software
The ASIC/SOC Silicon Verification Engineer will contribute to verification methodology, own execution for subsystem and chip-level verification, and create testbenches and tests. Responsibilities include planning reviews on verification progress towards silicon milestones and ensuring verification closure.
10 Hours Ago
Mountain View, CA, USA
Artificial Intelligence • Hardware • Software
Silicon Physical Design Engineers at MatX develop high-performance silicon for various products, overseeing the entire Physical Design process from RTL to GDSII. Responsibilities include contributing to design methodology, managing chip-level deliverables, and collaborating with design and verification teams to achieve optimal performance, power, and area results.