Silicon Design-for-Test (DFT) Engineer

Posted 12 Days Ago
Be an Early Applicant
Mountain View, CA
Mid level
Artificial Intelligence • Hardware • Software
The Role
The Silicon Design-for-Test (DFT) Engineer will implement DFT functions for silicon products, including integrating DFT interfaces, executing verification, and collaborating on physical design. Responsibilities include utilizing DFT automation tools and working with partners for production readiness, focusing on high-performance silicon for GenAI applications.
Summary Generated by Built In

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design-For-Test (DFT) engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies in leading-edge process nodes.

In this role you will:

  • Execute MatX’s DFT implementation/verification and collaborate on physical design methodology from RTL to GDS.
  • Integrate DFT interfaces from IP blocks and develop pattern porting flow.
  • Identify and execute effective & efficient DFT solutions based on chip architecture.
  • Work closely with the design, verification and physical design co-owners of the subsystem/block and top-level on DFT verification and physical design considerations to deliver best-in-class performance-power-area results
  • Work with vendor and test partners to bring up test program on silicon towards production and NPI

Key Experience and requirements for this role:

  • DFT implementation (MBIST and At-speed Scan) and execution on large and complex ASICs and SOCs to production silicon
  • Experience with latest DFT technologies (like IJTAG, Streaming Scan, efficient memory repair)
  • DFT Flow automation and hands on experience with Tessent DFT & Fusion Compiler
  • Experience of working with a third-party design services partners to deliver tapeout-ready designs with DFT
  • Experience/familiarity of integration of PHY DFT interfaces
  • Knowledge of post-silicon DFT pattern bring-up

Compensation

  • The US base salary for this full-time position is $120,000 - $400,000 + equity

Benefits

  • Commuter stipend available for employees within 60 minutes of the office
  • 401(k) with contribution matching
  • Health, vision, and dental insurance
  • Life and AD&D insurance

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

Top Skills

Asic
Soc
The Company
HQ: Mountain View, CA
19 Employees
On-site Workplace

What We Do

MatX designs hardware tailored for the world’s best AI models: We dedicate every transistor to maximizing performance for large models. For these models, we deliver 10× more computing power, enabling AI labs to make models an order of magnitude smarter and more useful. Our hardware would make it possible to train GPT-4 and run ChatGPT, but on the budget of a small startup.

A world with more widely available intelligence is a happier and more prosperous world—picture people of all socioeconomic levels having access to an AI staff of specialist MDs, tutors, coaches, advisors, and assistants.

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