Top Hybrid C++ Jobs in Santa Cruz, CA

The Multi-Chiplet Fabric Performance Engineer will define multi-chiplet interconnection solutions, create performance models for bandwidth estimation, and debug performance issues. This role involves collaborative work on architecture and implementation, ensuring the performance of RTL designs aligns with targets, while also developing tests for model quality.

As Fabric/Interconnect Architect, you will develop and specify internal interconnect architecture, covering both coherent and non-coherent systems. You will collaborate with the Silicon team to ensure power, performance, and area requirements are met while reviewing validation plans for functionality and performance.

As a Memory Subsystem Architect, you will specify memory subsystem architecture, working closely with software and silicon teams to define performance, power, and area requirements. Your role involves collaborating with industry groups and memory vendors, contributing to micro-architecture specifications, and conducting technical investigations for validation.