Top Perl Jobs
As a Senior Software Engineer, you will design, develop, and maintain software applications for mission-critical laboratory operations, collaborate with teams for alignment on architecture, and ensure high-quality delivery using agile methodologies while leading technical discussions and evaluating new technologies.
The Senior Storage Engineer manages and maintains the Storage Area Network and data backup infrastructure, ensuring reliability and capacity. The role requires expertise in Windows and Linux storage components, protocol handling, automation tools, and scripting. Additionally, the engineer develops APIs, participates in capacity planning, and contributes to troubleshooting complex storage issues in a mission-critical environment.
The Principal Physical Design Engineer will lead chip-level Place and Route activities ensuring high-performance designs. This role involves hands-on design work, technical leadership, tool optimization, and collaboration with various teams while mentoring junior engineers in the semiconductor field.
The Senior Staff Physical Design Engineer will focus on the physical design and methodology for high-performance processor chips. Responsibilities include synthesis, place and route, timing analysis, and collaborating with various teams to resolve timing and logic issues, ensuring successful tapeouts.
The Principal Design Verification Engineer at Marvell will verify complex SoCs through RTL and gate level simulation, develop verification environments using System Verilog and UVM, manage tests and regression failures, and collaborate with teams to implement verification test plans.
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The Sr Staff Enterprise Application Engineer will lead and coordinate PLM discussions, develop enterprise tools, evaluate technology trends, mentor teams, and ensure alignment between enterprise strategies and business goals, alongside hands-on POC development and application design.
As an Enterprise Application Engineer, you will develop and implement architectural solutions, analyze data, participate in governance, and mentor team members while focusing on custom CAD applications and infrastructure solutions.
Silicon Physical Design Engineers at MatX develop high-performance silicon for various products, overseeing the entire Physical Design process from RTL to GDSII. Responsibilities include contributing to design methodology, managing chip-level deliverables, and collaborating with design and verification teams to achieve optimal performance, power, and area results.
The Senior Software Engineer will design, build, and maintain network automation tools, leveraging scripting languages and open-source automation tools to enhance network operations. Responsibilities include refactoring existing tools, collaborating with cross-functional teams, and managing projects from inception to delivery while staying updated on emerging technologies.
Responsible for researching, designing, and deploying network technologies for Fiber to the Premise broadband infrastructures. Collaborate with multiple departments to configure and implement IP routing and access networks, provide technical expertise, and develop architectural designs and documents. Engage with clients and partners, support sales efforts, and evaluate new technologies to enhance service delivery.
The Senior Physical Design Engineer will be responsible for the physical design of high-performance CPUs and AI architectures, overseeing tasks from synthesis through to tapeout. They will collaborate closely with various teams, ensure timing closure, and employ innovative design techniques for performance enhancement.
The CPU Core Performance Verification Engineer will develop test plans and stimuli for performance verification of CPUs, perform simulations and debugging, work on industry standard and open-source workloads, and collaborate with design and architecture teams to ensure CPU performance and quality.
Tenstorrent is seeking a CPU core level feature/testplan verification engineer responsible for ISA and microarchitectural verification. Responsibilities include functional verification, testplanning, stimulus development, and regression debug. The role is hybrid and based in Austin, TX or Santa Clara, CA.
The SLT Test Engineer will own the system-level testing to enhance the quality and reliability of GroqCloud by designing and validating tests, collaborating with other teams, and automating SLT tests for improved manufacturing processes.
The ASIC Design Engineer at Infinera will be responsible for controlling subsystem development in large mixed signal ASICs, defining control plane specifications, optimizing micro-architecture, and providing layout support for quality product development. The role requires solid ASIC design skills and experience with various protocols and interfaces.
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