Test Engineering Lead

Posted 14 Days Ago
Be an Early Applicant
Mountain View, CA
Senior level
Hardware • Software
The Role
As a Test Development Lead, you will develop test plans and solutions for ACF-S silicon, design ATE hardware, implement testing methodologies, ensure signal integrity, and collaborate with multiple teams to guarantee high-quality products while bridging gaps in manufacturing tests.
Summary Generated by Built In

Enfabrica is at the forefront of building cutting edge networking silicon and system software to drive the revolution in AI and accelerated computing infrastructure at scale. The Lead Silicon Architect role will drive architecture/microarchitecture definition and specification, tradeoffs, modeling, and drive the deliverables needed for design and implementation of our next generation Accelerated Compute Fabric chip.
Test Engineering Lead
Qualifications:

  • ​​​​​​10+ years of experience in ATE test developmentExpertise in designing complex, highspeed and high performance ATE hardware
  • Experience with testing high speed interfaces (Ethernet, PCIe, DDR5 etc.)
  • Strong knowledge of SCAN and BIST DFT test methodologies and debugging
  • Proficiency on Advantest 93K ATE platform (Smartscale, Exascale etc.)
  • Experience in sustaining System Level Testing setups, hardware and software
  • Prior knowledge on ATE-SLT correlation, bridging the test coverage gaps to reduce the overall cost of test
  • Excellent problem-solving skills


Responsibilities:

  • As a Test Development Lead in the Silicon/Hardware Operations team, you will be responsible for developing test plans and solutions for Accelerated Compute Fabric (ACF-S) silicon at Enfabrica.
  • Test solutions involve designing, developing, implementing ATE methodologies for ACF-S which includes writing test programs, debugging various tests, creating efficient test flow to support successful silicon development and manufacturing.
  • You will be responsible for designing the ATE Probe Hardware, Final Test hardware and Reliability hardware, ensuring they meet the high-speed performance and test coverage requirements.
  • You will be responsible for developing characterization tests on the ATE and leading the PVT characterization effort to ensure product margins before volume customer shipments.
  • You will collaborate with the Packaging/SI-PI engineering team within Operations to ensure all test hardware meets the signal integrity requirements
  • You will work closely with Design/Software/Firmware/System teams to ensure the manufacturing test requirements deliver the highest quality and performance for Enfabrica’s products.
  • Define DFT requirements for Enfabrica’s next generation products and align the DFT requirements to company’s roadmap
  • Work closely with Design, System and SW teams to ensure testability of the silicon and meet customer specifications
  • Sustain SLT test and bridge the manufacturing test coverage gap between ATE and SLT with comprehensive correlation efforts
  • Prevent the shipment of underperforming units are shipped by implementing “Best-in-Class” test methodology across ATE and SLT
  • Lead and execute all test engineering activities related to New Product Introduction (NPI)

About Us:
Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics.

Top Skills

Ate
Ddr5
Ethernet
Pcie
The Company
HQ: Mountain View, CA
77 Employees
On-site Workplace
Year Founded: 2019

What We Do

We develop groundbreaking hardware, software, and system technologies that solve the critical bottlenecks in next-generation computing workloads - at any scale - across hyperscale cloud, edge, enterprise, 5G/6G, and automotive infrastructure.

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