The Lead Design Engineer will coordinate staff for test chip bringup and validation, oversee customer support, manage Jira ticket closures, and improve IP quality while addressing silicon issues.

The Principal Design Engineer at Cadence will work on high-speed Serdes and memory interface circuits, lead complex IP projects, manage cross-functional teams, mentor junior engineers, and ensure excellent communication while solving complex design challenges in advanced technology nodes.

The Lead Design Engineer will design and lead the development of high-speed IPs, focusing on analog domains. Responsibilities include analog design, layout, digital design, documentation, and silicon validation, as well as customer interactions. Candidates should have hands-on experience in analog IP development and effective communication skills.

The Principal Design Engineer will lead the design and innovation of high-speed Serdes and memory interface circuits, mentor junior engineers, and manage complex projects while ensuring effective communication and cross-functional collaboration.

The Lead FrontEnd Methodology Engineer at Cadence will enhance and manage the infrastructure and automation for RTL development and design-verification teams across multiple server farms. The role involves automating error reporting, monitoring regression trends, and supporting users while working with several technologies including cloud services and scripting languages.

The Sr Staff Systems Engineer at Cadence will support and manage the compute farm environment, develop server farm tools, and collaborate with R&D teams to optimize workflow productivity across global locations. Expertise in cloud solutions and scripting in Linux is essential.

As a Lead Solutions Engineer, you will collaborate with customers to develop Virtual/Hybrid prototypes, optimize system models, and integrate these into larger systems while assisting in debugging software issues. This role involves significant interaction with customers and requires a deep understanding of software and system validation.

As a Principal Design Engineer at Cadence, you will be responsible for AMS design specifically focusing on high-speed Memory PHYs. You will define designs, mentor team members, participate in cross-functional discussions, and ensure design quality and project timelines while improving methodologies for efficiency.

We are seeking a Principal Software Engineer with experience in Electronic Design Automation (EDA), particularly in emulation. The candidate should have strong knowledge of C++ and SystemVerilog, along with familiarity with protocols, preferably MIPI protocols. The role focuses on making significant contributions to technology and solving complex problems.

The Application Engineer will provide post-sales technical consultation for Cadence's digital and sign-off products. Responsibilities include resolving complex issues, leveraging tool capabilities, guiding software implementation, and mentoring team members, while contributing to product improvement initiatives.

As a Principal Application Engineer at Cadence, you will work closely with customers, providing post-sales technical consultation for digital and sign-off domain products. Responsibilities include resolving complex issues, creating impactful knowledge content, leading a small team, and innovating design solutions. The role emphasizes technical leadership and collaboration with product teams.

The Principal Software Engineer will focus on providing software innovations to enhance Protium's Compile and Place & Route Time in FPGA Emulation/Prototyping. Key responsibilities include leveraging C++ and Python/Tcl to optimize processes and improve the overall performance of the Protium product.

The Lead Product Engineer at Cadence focuses on driving the development of UCIe-related products and technologies, primarily in verification. They are responsible for product adoption, technical support, customer training, and translating high-level requirements into technical specifications. This role necessitates collaboration with multiple teams and an understanding of customer design and verification flows.

The Lead Application Scientist will lead technical presentations, assist clients with OpenEye's molecular design platform, and collaborate with science and development teams. Responsibilities include customer support, research partnerships, and attending conferences while requiring a PhD in a related field and strong communication skills.

As a Lead Design Engineer at Cadence, your responsibilities include performing physical layer electrical validation on high speed SERDES IP, designing hardware and software infrastructure for validation, implementing rigorous testing compliance, and debugging silicon issues to generate test reports.

The role requires a Lead Full Stack Cloud Engineer with 8-10 years of experience to build complex applications using technologies like Angular, Java, and cloud services. Responsibilities include integrating applications, unit testing, and deploying on cloud environments, while ensuring data sharing and working in a Linux environment.

The Principal Design Engineer at Cadence will lead major blocks of Memory PHY Layout design, perform hands-on design of critical analog and high-speed layout blocks, coordinate design work with circuit leads and layout contractors, and participate in layout reviews.

The Lead Software Engineer at Cadence will focus on developing and improving the Protium P&R tool, enhancing QoR and implementation of features to reduce P&R time, while collaborating closely with users to deploy new functionalities. Strong communication skills and a capability to learn quickly are essential.

The Associate HR Representative will support HR administration tasks including onboarding new hires, maintaining employee files, coordinating interviews, and assisting with payroll. They will collaborate with hiring managers and facilitate training sessions, ensuring smooth HR processes within the organization.

The Lead Software Engineer will optimize global placement in Cadence's Innovus Place & Route product, focusing on electronic design automation. The role requires strong problem-solving skills in software development, specifically C/C++ in a Linux environment, along with a deep understanding of data structures, algorithms, and potential GPU programming. The candidate will contribute to high-performance teams that impact the chip industry and customer solutions.