Sr. Timing Signoff and Methodology Lead

Job Details:

Job Description: 

When you join Intel, you become part of a global organization with big ambitions. Our people have had a profound influence on the world by creating radical innovations that revolutionize the way we live.

 We are driven by our purpose: To create world-changing technology that improves the life of every person on the planet. We develop technologies that bring down barriers and enable tomorrow’s greatest scientific breakthroughs and cultural achievements.

Responsibilities include but are not limited to:

• Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at full chip/block level for SoCs.
• Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks.
• Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.
• Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning.
• Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning.
• Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.
• Understanding of DFT (design for testability) logic and hands-on experience in design closure.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications:

• Bachelor's degree in Electrical / Computer Engineering, Computer Science or in a STEM related field of study.
• 8+ years of timing verification experience.

Preferred Qualifications:

• Master's degree
• 10+ years STA hands on experience.
• Server experience.

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Colorado, Fort Collins

Additional Locations:US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro, US, Texas, Austin

Business group:The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

The application window for this job posting is expected to end by 05/31/2025